公开(公告)号：US3898478A

公开(公告)日：1975-08-05

申请号：US42851473

申请日：1973-12-26

Applicant: BENDIX CORP

Inventor： RUDOLPH JOHN D ,  SOLOMON JOSEPH A

IPC: H03D1/00 ,  H03K5/003 ,  H04B1/10

CPC classification number: H03D1/00 ,  H03K5/003

Abstract: For use with analog a.c.-to-analog d.c. conversion systems or the like employing balanced demodulators for reducing settling time i.e., the interval between application of a.c. superimposed on d.c. and the provision of a d.c. analog of the superimposed a.c., means for introducing an independent keying signal to force demodulation during part of the settling time.

Abstract translation: 用于模拟直流到模拟直流 转换系统等采用平衡解调器来减少建立时间，即应用交流电的间隔。 叠加在d.c. 并提供一个d.c. 叠加的交流电流的模拟，用于引入独立的键控信号以在部分稳定时间期间迫使解调的装置。