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公开(公告)号：US20240221697A1
公开(公告)日：2024-07-04
申请号：US17923946
申请日：2021-11-16
发明人： Junwei ZHANG , Feifei WANG , Wei HAO , Wengang SU , Kaimin YIN , Xingce SHANG , Taotao DUAN , Liguang GENG , Huangfei CHA , Yu DENG
IPC分类号： G09G3/36 , G02F1/1335 , G02F1/13357 , H01L25/16
CPC分类号： G09G3/3611 , G02F1/133603 , G02F1/133612 , G09G2310/0243 , G09G2330/00 , H01L25/167
摘要： A driver circuit includes a logic control component and a plurality of pins coupled to the logic control component. The plurality of pins include a clock pin, a data pin and at least two output pins. The clock pin is configured to receive a clock signal. The data pin is configured to receive, under control of the logic control component, a data signal in a period of an active level of the clock signal. The logic control component is configured to generate a driving control signal corresponding to each output pin according to the data signal, so as to control an electrical signal flowing through the output pin.
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2.发明公开公开(公告)号：US20230282172A1
公开(公告)日：2023-09-07
申请号：US18016716
申请日：2021-06-21
发明人： Kaimin YIN , Wei HAO , Lingyun SHI , Wenchieh HUANG , Feifei WANG , Wengang SU , Rui SHI , Xingce SHANG , Junwei ZHANG , Taotao DUAN
IPC分类号： G09G3/3283
CPC分类号： G09G3/3283
摘要： The present disclosure provides a driver circuit, a driving method of the driver circuit, an array substrate and a display device, belonging to the field of display technology. The driver circuit provided by the present disclosure includes a logic control module, a data pin and at least two output pins. The data pin is configured to receive driving data. The logic control module is configured to generate driving control signals in a one-to-one correspondence with the at least two output pins according to the driving data. The driving control signals are configured to control the current flowing through the corresponding output pins.
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