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公开(公告)号:US20210241697A1
公开(公告)日:2021-08-05
申请号:US17234873
申请日:2021-04-20
发明人: Tieshi WANG , Xueling GAO , Zhiqiang XU , Chengchung YANG , Haoran LIU
IPC分类号: G09G3/3258 , G09G3/3266 , G09G3/3233
摘要: A method of driving a pixel includes providing a driving transistor having a first end connected to a first node, a control end connected to a second node, and a second connected to the third node end; a writing circuit connected a data signal end, a first scanning end and the first node; a first control circuit connected to a first power end, a light emitting control end and the first node; a reset circuit connected to a reference signal end, a second scanning end, and the second node; a compensation circuit connected between the second node and the third node; a second control circuit connected to the third node, a light emitting element, and the light emitting control end; and an energy storage circuit connected between the first power end and the second node. The second end of the light emitting element receives a second voltage signal.
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公开(公告)号:US20220246098A1
公开(公告)日:2022-08-04
申请号:US17726875
申请日:2022-04-22
发明人: Tieshi WANG , Xueling GAO , Zhiqiang XU , Chengchung YANG , Haoran LIU
IPC分类号: G09G3/3258 , G09G3/3233 , G09G3/3266
摘要: A circuit for driving a pixel includes a driving transistor having a first end connected to a first node, a control end connected to a second node, and a second end connected to a third node; a writing circuit connected to a first scanning signal and the first node and configured to transmit a data signal to the first node; a reset circuit connected to a second scanning signal and configured to transmit a reference signal to the second node; a compensation circuit connected to a compensation control signal and configured to put through a connection between the second end and the control end of the driving transistor in response to the compensation control signal, wherein the compensation control signal is different from the first scanning signal and the second scanning signal; and an energy storage circuit connected between a first power end and the second node.
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