Epitaxial Wafer and Manufacturing Method Thereof
    1.
    发明申请
    Epitaxial Wafer and Manufacturing Method Thereof 有权
    外延晶圆及其制造方法

    公开(公告)号:US20130052807A1

    公开(公告)日:2013-02-28

    申请号:US13663000

    申请日:2012-10-29

    CPC classification number: H01L33/382 H01L33/007 H01L2933/0016

    Abstract: A semiconductor device comprises a substrate; a conductive layer deposited on a substrate, the conductive layer being patterned to include a first pattern, the first pattern including a major surface and a plurality of grids defined in the major surface, the major surface including first lines and a connecting portion, wherein the connecting portion is connected to an electrode; and an epitaxial layer disposed on the conductive layer, covering the grids and the first line between the adjacent grids.

    Abstract translation: 半导体器件包括衬底; 沉积在衬底上的导电层,所述导电层被图案化以包括第一图案,所述第一图案包括主表面和限定在所述主表面中的多个栅格,所述主表面包括第一线和连接部分,其中, 连接部分连接到电极; 以及设置在导电层上的外延层,覆盖相邻网格之间的网格和第一线。

    Epitaxial wafer and manufacturing method thereof
    2.
    发明授权
    Epitaxial wafer and manufacturing method thereof 有权
    外延晶片及其制造方法

    公开(公告)号:US08859315B2

    公开(公告)日:2014-10-14

    申请号:US13663000

    申请日:2012-10-29

    CPC classification number: H01L33/382 H01L33/007 H01L2933/0016

    Abstract: A semiconductor device comprises a substrate; a conductive layer deposited on a substrate, the conductive layer being patterned to include a first pattern, the first pattern including a major surface and a plurality of grids defined in the major surface, the major surface including first lines and a connecting portion, wherein the connecting portion is connected to an electrode; and an epitaxial layer disposed on the conductive layer, covering the grids and the first line between the adjacent grids.

    Abstract translation: 半导体器件包括衬底; 沉积在衬底上的导电层,所述导电层被图案化以包括第一图案,所述第一图案包括主表面和限定在所述主表面中的多个栅格,所述主表面包括第一线和连接部分,其中, 连接部分连接到电极; 以及设置在导电层上的外延层,覆盖相邻网格之间的网格和第一线。

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