Abstract:
Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding.
Abstract:
Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding.
Abstract:
Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission.
Abstract:
Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission.
Abstract:
Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission.
Abstract:
Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding.
Abstract:
Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission.
Abstract:
Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding.
Abstract:
Quasi-cyclic LDPC (Low Density Parity Check) code construction is presented that ensures no four cycles therein (e.g., in the bipartite graphs corresponding to the LDPC codes). Each LDPC code has a corresponding LDPC matrix that is composed of square sub-matrices, and based on the size of the sub-matrices of a particular LDPC matrix, then sub-matrix-based cyclic shifting is performed as not only a function of sub-matrix size, but also the row and column indices, to generate CSI (Cyclic Shifted Identity) sub-matrices. When the sub-matrix size is prime (e.g., each sub-matrix being size q×q, where q is a prime number), then it is guaranteed that no four cycles will exist in the resulting bipartite graph corresponding to the LDPC code of that LDPC matrix. When q is a non-prime number, an avoidance set can be used and/or one or more sub-matrices can be made to be an all zero-valued sub-matrix.
Abstract:
Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal.