公开(公告)号：US20190324815A1

公开(公告)日：2019-10-24

申请号：US16502300

申请日：2019-07-03

Applicant: Beckhoff Automation GmbH

Inventor： Richard Kümmel ,  Manuel Bettenworth ,  Henning Zabel ,  Jan Achterberg ,  Dirk Janssen

IPC: G06F9/50 ,  G06F9/22 ,  G06F9/30 ,  G06F9/38

Abstract: To control a technical process comprising a control task for independently controllable modules, modules are each assigned to a computing core on a controller with a plurality of computing cores. The technical process is connected to the controller via at least one communication connection. In a first time segment, the controller provides read-in input data of the modules for the respectively associated computing core. Subsequently, synchronization of the computing cores to which modules are assigned is carried out by the controller. In a second time segment, the computing cores process the input data of the modules to generate output data for the modules, wherein each computing core signals the end of processing. As soon as all computing cores have signaled the end of processing, the output data are provided in a third time segment by the controller in order to be provided to the modules on the communication connection.

公开(公告)号：US11327800B2

公开(公告)日：2022-05-10

申请号：US16502300

申请日：2019-07-03

Applicant: Beckhoff Automation GmbH

Inventor： Richard Kümmel ,  Manuel Bettenworth ,  Henning Zabel ,  Jan Achterberg ,  Dirk Janssen

IPC: G06F9/46 ,  G06F9/50 ,  G05B19/042 ,  G06F9/52

Abstract: To control a technical process comprising a control task for independently controllable modules, modules are each assigned to a computing core on a controller with a plurality of computing cores. The technical process is connected to the controller via at least one communication connection. In a first time segment, the controller provides read-in input data of the modules for the respectively associated computing core. Subsequently, synchronization of the computing cores to which modules are assigned is carried out by the controller. In a second time segment, the computing cores process the input data of the modules to generate output data for the modules, wherein each computing core signals the end of processing. As soon as all computing cores have signaled the end of processing, the output data are provided in a third time segment by the controller in order to be provided to the modules on the communication connection.