公开(公告)号：US11748250B2

公开(公告)日：2023-09-05

申请号：US17536475

申请日：2021-11-29

Applicant: Beijing Horizon Robotics Technology Research and Development Co., Ltd.

Inventor： Jianjun Li ,  Meng Yao ,  Zhenjiang Wang ,  Yu Zhou

IPC: G06F12/02 ,  G06N3/063

CPC classification number: G06F12/02 ,  G06N3/063

Abstract: This application discloses a data processing method and apparatus, an electronic device, and a storage medium. When execution is performed at an operation layer of a neural network model, based on a pre-stored buffer allocation relationship, a first address range for cyclic addressing is set for a first buffer corresponding to input data and a second address range for cyclic addressing is set for a second buffer corresponding to an output result. Subsequently, cyclic addressing can be performed in the first buffer based on the first address range for cyclic addressing, to read the input data for the operation layer; and cyclic addressing can be performed in the second buffer based on the second address range for cyclic addressing, to write the output result of the operation layer into the second buffer. In this way, efficiency of buffer utilization can be effectively improved, and further operation efficiency for the model is improved.

公开(公告)号：US20220197786A1

公开(公告)日：2022-06-23

申请号：US17536475

申请日：2021-11-29

Applicant: Beijing Horizon Robotics Technology Research and Development Co., Ltd.

Inventor： Jianjun Li ,  Meng Yao ,  Zhenjiang Wang ,  Yu Zhou

IPC: G06F12/02 ,  G06N3/063

Abstract: This application discloses a data processing method and apparatus, an electronic device, and a storage medium. When execution is performed at an operation layer of a neural network model, based on a pre-stored buffer allocation relationship, a first address range for cyclic addressing is set for a first buffer corresponding to input data and a second address range for cyclic addressing is set for a second buffer corresponding to an output result. Subsequently, cyclic addressing can be performed in the first buffer based on the first address range for cyclic addressing, to read the input data for the operation layer; and cyclic addressing can be performed in the second buffer based on the second address range for cyclic addressing, to write the output result of the operation layer into the second buffer. In this way, efficiency of buffer utilization can be effectively improved, and further operation efficiency for the model is improved.