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1.
公开(公告)号:US20230342415A1
公开(公告)日:2023-10-26
申请号:US18192548
申请日:2023-03-29
Inventor: Yinan ZHANG , Delin LI , Jianjun LI
IPC: G06F17/15
CPC classification number: G06F17/153
Abstract: Disclosed are a feature extraction method and apparatus for a three-dimensional feature map, a storage medium, and an electronic device. The method includes: determining an overlay parameter based on depth information of a three-dimensional feature map to be processed; decomposing the three-dimensional feature map into a plurality of target two-dimensional feature maps based on the depth information and the overlay parameter; performing two-dimensional convolution processing on each of the plurality of target two-dimensional feature maps to obtain a plurality of initial feature maps; and determining a target feature map corresponding to the three-dimensional feature map based on the plurality of initial feature maps.
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2.
公开(公告)号:US20230409886A1
公开(公告)日:2023-12-21
申请号:US18247408
申请日:2022-02-10
Inventor: Zhuoran ZHAO , Kai YU , Chang HUANG , Zhenjiang WANG , Jianjun LI , Delin LI , Yinan ZHANG
IPC: G06N3/0464
CPC classification number: G06N3/0464
Abstract: The present disclosure provides a method and apparatus for deconvolving feature data using convolution hardware. The method includes: reading a feature map and deconvolution kernel into on-chip memory, and padding zeroes to the feature map; determining convolution kernels based on the deconvolution kernel; removing a row and/or column of each convolution kernel whose elements all are invalid weights, to obtain an optimized convolution kernel, and removing a corresponding row and/or column in the zero-padded feature map to obtain an corresponding optimized feature map; convolving each optimized convolution kernel with corresponding optimized feature map using the multiply-add array, to obtain convolutional outputs; and interleaving and synthesizing the convolutional outputs to obtain an interleaving synthetic output including at least a deconvolutional output corresponding to the feature map and deconvolution kernel. The method reduces hardware complexity, chip area and power consumption, and many invalid operations, improving operating efficiency of convolution hardware.
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