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1.发明申请AN IMPROVED RECEIVER HAVING FULL SIGNAL PATH DIFFERENTIAL OFFSET CANCELLATION CAPABILITIES 失效具有完整信号路径的改进接收器差分偏移消除能力公开(公告)号：US20050212564A1
公开(公告)日：2005-09-29
申请号：US10906988
申请日：2005-03-15
CPC分类号： H03F3/45775 , G11C27/026
摘要： There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.
摘要翻译： 描述了一种改进的接收机，其首先包括模拟输入放大器，采样保持差分电路和串联连接的两级差分比较器，其中第一级由两个比较器和一个比较器的第二级组成。 通过用专用控制逻辑产生的信号正确激活开关，输入差分信号在取样和保持电路中被采样，以产生第一和第二差分信号。 第一差分信号保持第一状态，第二差分信号传播第二状态。 结果，由第二比较器级输出的信号反映差分偏移减去偏移补偿。
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2.发明授权Differential sampling circuit for generating a differential input signal DC offset 失效用于产生差分输入信号DC偏移的差分采样电路公开(公告)号：US06946986B2
公开(公告)日：2005-09-20
申请号：US10738347
申请日：2003-12-17
CPC分类号： G11C27/026
摘要： A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin−) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.
摘要翻译： 差分采样电路配置在差分运算放大器周围，并且设置有一对开关电容器网络，每个开关电容器网络包括电路块，以在每个系统时钟周期产生差分输入信号DC偏移的实际值。 在前半周期，对差分输入信号对（Vin +，Vin-）进行采样，每个网络中的保持电容都被充电。 在第二个半周期期间，差分输入信号对被再次采样，并且保持电容进一步被充电。 在周期结束时，保持在保持电容器中的电荷被施加到差分运算放大器，使得差分输出信号等于实际差分输入信号DC偏移值。
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3.发明授权Receiver having full signal path differential offset cancellation capabilities 失效接收机具有全信号路径差分偏移消除功能公开(公告)号：US07180354B2
公开(公告)日：2007-02-20
申请号：US10906988
申请日：2005-03-15
IPC分类号： H03L5/00
CPC分类号： H03F3/45775 , G11C27/026
摘要： There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.
摘要翻译： 描述了一种改进的接收机，其首先包括模拟输入放大器，采样保持差分电路和串联连接的两级差分比较器，其中第一级由两个比较器和一个比较器的第二级组成。 通过用专用控制逻辑产生的信号正确激活开关，输入差分信号在取样和保持电路中被采样，以产生第一和第二差分信号。 第一差分信号保持第一状态，第二差分信号传播第二状态。 结果，由第二比较器级输出的信号反映差分偏移减去偏移补偿。
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4.发明申请Very High Speed Low Power Receiver Equalization System For Non-Return-To-Zero Transmission 审中-公开用于非归零传输的超高速低功耗接收器均衡系统公开(公告)号：US20080279271A1
公开(公告)日：2008-11-13
申请号：US11621229
申请日：2007-01-09
IPC分类号： H04L27/01
CPC分类号： H04L25/03878
摘要： A very high speed low power receiver equalization system for non-return-to-zero transmission is disclosed. The equalizer comprises a three stage architecture, preferably controlled by three main parameters, the low frequency gain controlled through Rfb, the peaking frequency settled by the capacitor Cfpk, and the variable peak boosting Gpk which provides the equalizer transfer function and the optimum controls of the signal gain characteristic in order to compensate the ISI at the receiver input and consequently allow High speed, reliable links.
摘要翻译： 公开了一种用于非归零传输的非常高速的低功率接收机均衡系统。 均衡器包括三级结构，优选由三个主要参数控制，通过Rfb控制的低频增益，由电容器Cfpk稳定的峰值频率以及提供均衡器传递函数的可变峰值升压Gpk以及最佳控制 信号增益特性，以补偿接收机输入端的ISI，从而允许高速，可靠的链路。
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