INTEGRATED DELAYED CLOCK FOR HIGH SPEED ISOLATED SPI COMMUNICATION
    1.
    发明申请
    INTEGRATED DELAYED CLOCK FOR HIGH SPEED ISOLATED SPI COMMUNICATION 有权
    用于高速隔离SPI通信的集成延迟时钟

    公开(公告)号:US20140266373A1

    公开(公告)日:2014-09-18

    申请号:US13841130

    申请日:2013-03-15

    IPC分类号: H03K3/011

    摘要: A system may include a plurality of isolators to transfer data signals across an isolation barrier, one of the signals including a clock signal. A delay circuit may be included to receive the clock signal and provide a delayed clock signal that lags the clock signal by an amount representing a delay across the isolation barrier. The delayed clock signal may be delayed by a round trip propagation delay over the isolation barrier. The delayed clock signal may be used as a reference to read data sent over the isolation barrier.

    摘要翻译: 系统可以包括多个隔离器以跨越隔离屏障传送数据信号,其中一个信号包括时钟信号。 可以包括延迟电路以接收时钟信号,并提供延迟时钟信号的延迟时钟信号,该延迟时钟信号表示跨隔离屏障延迟的量。 延迟的时钟信号可能被隔离屏障上的往返传播延迟延迟。 延迟时钟信号可以用作读取通过隔离屏障发送的数据的参考。