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1.发明申请Slave latch controlled retention flop with lower leakage and higher performance 有权从锁存控制保持触发器具有较低的泄漏和更高的性能公开(公告)号：US20090058484A1
公开(公告)日：2009-03-05
申请号：US11895853
申请日：2007-08-27
IPC分类号： H03K3/289
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/356147
摘要： In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.
摘要翻译： 在用于数据保持的方法和装置中，第一锁存器锁存数据输入端，耦合到第一锁存器的第二锁存器保持数据输入，而第一锁存器在备用电源模式下不起作用。 第二锁存器包括具有逆变器输入和反相器输出的第二锁存逆变器。 可以实现为三态逆变器的开关电路耦合到逆变器输出端，逆变器输入端和保持信号。 切换电路可在待机功率模式下操作，以响应于保持信号断言反相器输入处的逻辑状态。 逻辑状态与备用电源模式中保留的数据输入相一致。 备用电源可操作以将待机功率模式的电力提供给第二锁存逆变器，开关电路和保持输入。
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2.发明授权Slave latch controlled retention flop with lower leakage and higher performance 有权从锁存控制保持触发器具有较低的泄漏和更高的性能公开(公告)号：US07652513B2
公开(公告)日：2010-01-26
申请号：US11895853
申请日：2007-08-27
IPC分类号： H03K3/356
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/356147
摘要： In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.
摘要翻译： 在用于数据保持的方法和装置中，第一锁存器锁存数据输入端，耦合到第一锁存器的第二锁存器保持数据输入，而第一锁存器在备用电源模式下不起作用。 第二锁存器包括具有逆变器输入和反相器输出的第二锁存逆变器。 可以实现为三态逆变器的开关电路耦合到逆变器输出端，逆变器输入端和保持信号。 切换电路可在待机功率模式下操作，以响应于保持信号断言反相器输入处的逻辑状态。 逻辑状态与备用电源模式中保留的数据输入相一致。 备用电源可操作以将待机功率模式的电力提供给第二锁存逆变器，开关电路和保持输入。
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