Data processing
    1.
    发明授权

    公开(公告)号:US10198268B2

    公开(公告)日:2019-02-05

    申请号:US15182385

    申请日:2016-06-14

    Abstract: A processing element comprises a plurality of function units (16) operable to execute respective functions in dependence upon received instructions in parallel with one another. An instruction controller includes an instruction register (41) having a plurality of register entries, each of which is operable to store an instruction word therein, and a plurality of instruction pipelines (42). Each of the pipelines (42) is associated with a function unit (16), and is operable to deliver instructions to the function unit concerned for execution thereby. Each pipeline also includes a timing controller operable to receive timing information for a received instruction, and to determine an initial location in the pipeline into which the instruction is to be loaded, and an instruction handler operable to receive an instruction for the function unit associated with the instruction pipeline concerned, and to load that instruction into the initial location determined by the timing controller.

    Data processing
    4.
    发明授权

    公开(公告)号:US09990204B2

    公开(公告)日:2018-06-05

    申请号:US15182335

    申请日:2016-06-14

    CPC classification number: G06F9/3836 G06F9/30145 G06F9/30156 G06F9/3867

    Abstract: A processing element comprises a plurality of function units (16) operable to execute respective functions in dependence upon received instructions in parallel with one another. An instruction controller includes a plurality of instruction pipelines (42). Each of the pipelines (42) is associated with a function unit (16) of the processing element, and is operable to deliver instructions to the function unit concerned for execution thereby. Each pipeline also includes a timing controller operable to receive timing information for a received instruction, and to determine an initial location in the pipeline into which the instruction is to be loaded, and an instruction handler operable to receive an instruction for the function unit associated with the instruction pipeline concerned, and to load that instruction into the initial location determined by the timing controller.

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