公开(公告)号：US08189792B2

公开(公告)日：2012-05-29

申请号：US12005680

申请日：2007-12-28

申请人： Brent Boswell ,  Kirk Yap ,  Gilbert Wolrich ,  Wajdi Feghali ,  Vinodh Gopal ,  Srinivas Chennupaty ,  Makaram Raghunandan

发明人： Brent Boswell ,  Kirk Yap ,  Gilbert Wolrich ,  Wajdi Feghali ,  Vinodh Gopal ,  Srinivas Chennupaty ,  Makaram Raghunandan

IPC分类号： G06F21/00

CPC分类号： H04L9/0631 ,  H04L2209/125

摘要： In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括处理器，其具有响应于第一和第二轮微操作执行一轮加密算法以在第一和第二列列上执行循环的逻辑，其中该逻辑包括半数的双数据通路 加密算法宽度（或更小）的宽度。 可以使用附加逻辑来组合第一和第二轮微操作的结果以获得圆形结果。 描述和要求保护其他实施例。

公开(公告)号：US20090168999A1

公开(公告)日：2009-07-02

申请号：US12005680

申请日：2007-12-28

申请人： Brent Boswell ,  Kirk Yap ,  Gilbert Wolrich ,  Wajdi Feghali ,  Vinodh Gopal ,  Srinivas Chennupaty ,  Makaram Raghunandan

发明人： Brent Boswell ,  Kirk Yap ,  Gilbert Wolrich ,  Wajdi Feghali ,  Vinodh Gopal ,  Srinivas Chennupaty ,  Makaram Raghunandan

IPC分类号： H04L9/28 ,  H04L9/00

CPC分类号： H04L9/0631 ,  H04L2209/125

摘要： In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括处理器，其具有响应于第一和第二轮微操作执行一轮加密算法以在第一和第二列列上执行循环的逻辑，其中该逻辑包括半数的双数据通路 加密算法宽度（或更小）的宽度。 可以使用附加逻辑来组合第一和第二轮微操作的结果以获得圆形结果。 描述和要求保护其他实施例。

公开(公告)号：US20140095845A1

公开(公告)日：2014-04-03

申请号：US13631807

申请日：2012-09-28

申请人： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Kirk Yap

发明人： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Kirk Yap

IPC分类号： G06F9/30

摘要： An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.

摘要翻译： 描述了一种用于在流水线处理器中执行有效的布尔运算的装置和方法，其在一个实施例中不本地支持三个操作数指令。 例如，根据本发明的一个实施例的处理器包括：一组用于存储打包操作数的寄存器; 用于执行单个指令的布尔运算逻辑，其使用打包在该组寄存器中的三个或更多个源操作数，布尔运算逻辑读取至少三个源操作数，并且立即值对三个源操作数执行布尔运算，其中， 布尔操作包括：组合从三个操作数中的每一个读取的位以形成立即值的索引，该索引标识立即值内的位位置; 从识别的位置读取该位从立即值; 并将来自所识别的立即值的比特位置的比特存储在目的地寄存器中。

公开(公告)号：US20100205455A1

公开(公告)日：2010-08-12

申请号：US12368196

申请日：2009-02-09

申请人： Vinodh Gopal ,  Kirk Yap ,  Gilbert Wolrich ,  Wajdi Feghali ,  Robert Ottavi ,  Sean Gulley

发明人： Vinodh Gopal ,  Kirk Yap ,  Gilbert Wolrich ,  Wajdi Feghali ,  Robert Ottavi ,  Sean Gulley

IPC分类号： H04L9/00

CPC分类号： G09C1/00 ,  H04L9/0637 ,  H04L2209/12

摘要： An embodiment includes at least one processing unit to perform at least first and second sets of diffusion-related operations to produce a resulting block from a data block, and that includes at least one stage and at least one other stage. The at least one stage is to select one of first operands and second operands input to the at least one other stage. The first and second operands are respectively associated with the first and second sets of operations, respectively. The at least one other stage involves arithmetic and logical operations common to both the first and second sets of operations. At least one other processing unit is to perform at least one set of cryptographic-related operations (different, at least in part, from the first and second sets of operations) on at least one of (1) another block to produce the data block and (2) the resulting block.

摘要翻译： 一个实施例包括至少一个处理单元，用于执行至少第一和第二组扩散相关操作以从数据块产生结果块，并且其包括至少一个阶段和至少一个其他阶段。 所述至少一个级是选择输入至少一个其他级的第一操作数和第二操作数之一。 第一和第二操作数分别分别与第一和第二组操作相关联。 所述至少一个其他阶段涉及对于第一和第二组操作共同的算术和逻辑运算。 至少一个其他处理单元将在（1）另一个块中的至少一个上执行至少一组密码相关操作（至少部分地不同于第一和第二组操作），以产生数据块 和（2）得到的块。

公开(公告)号：US08363828B2

公开(公告)日：2013-01-29

申请号：US12368196

申请日：2009-02-09

申请人： Vinodh Gopal ,  Kirk Yap ,  Gilbert Wolrich ,  Wajdi Feghali ,  Robert Ottavi ,  Sean Gulley

发明人： Vinodh Gopal ,  Kirk Yap ,  Gilbert Wolrich ,  Wajdi Feghali ,  Robert Ottavi ,  Sean Gulley

IPC分类号： G06F21/00

CPC分类号： G09C1/00 ,  H04L9/0637 ,  H04L2209/12

摘要： An embodiment includes at least one processing unit to perform at least first and second sets of diffusion-related operations to produce a resulting block from a data block, and that includes at least one stage and at least one other stage. The at least one stage is to select one of first operands and second operands input to the at least one other stage. The first and second operands are respectively associated with the first and second sets of operations, respectively. The at least one other stage involves arithmetic and logical operations common to both the first and second sets of operations. At least one other processing unit is to perform at least one set of cryptographic-related operations (different, at least in part, from the first and second sets of operations) on at least one of (1) another block to produce the data block and (2) the resulting block.

摘要翻译： 一个实施例包括至少一个处理单元，用于执行至少第一和第二组扩散相关操作以从数据块产生结果块，并且其包括至少一个阶段和至少一个其他阶段。 所述至少一个级是选择输入至少一个其他级的第一操作数和第二操作数之一。 第一和第二操作数分别分别与第一和第二组操作相关联。 所述至少一个其他阶段涉及对于第一和第二组操作共同的算术和逻辑运算。 至少一个其他处理单元将在（1）另一个块中的至少一个上执行至少一组密码相关操作（至少部分地不同于第一和第二组操作），以产生数据块 和（2）得到的块。

公开(公告)号：US20160191238A1

公开(公告)日：2016-06-30

申请号：US14582707

申请日：2014-12-24

申请人： Kirk YAP ,  Gilbert Wolrich ,  Sudhir Satpathy ,  Sean Gulley ,  Vinodh Gopal ,  Sanu Mathew ,  Wajdi Feghali

发明人： Kirk YAP ,  Gilbert Wolrich ,  Sudhir Satpathy ,  Sean Gulley ,  Vinodh Gopal ,  Sanu Mathew ,  Wajdi Feghali

IPC分类号： H04L9/08

CPC分类号： H04L9/0822 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

摘要： Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.

摘要翻译： 公开了用于SMS4加速硬件的发明的实施例。 在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮关键扩展。 密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。

公开(公告)号：US20080159528A1

公开(公告)日：2008-07-03

申请号：US11617418

申请日：2006-12-28

申请人： Wajdi Feghali ,  Stephanie Hirnak ,  Makaram Raghunandan ,  Yogesh Bansal ,  Kirk Yap ,  Gilbert M. Wolrich

发明人： Wajdi Feghali ,  Stephanie Hirnak ,  Makaram Raghunandan ,  Yogesh Bansal ,  Kirk Yap ,  Gilbert M. Wolrich

IPC分类号： H04L9/30 ,  H04L9/28

CPC分类号： H04L63/0485 ,  G06F9/30181 ,  G06F9/3879 ,  H04L63/08

摘要： In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 在一个实施例中，本公开提供了一种能够处理各种不同操作的方法。 根据一个实施例的方法可以包括将配置数据从共享存储器单元加载到硬件配置寄存器中，硬件配置寄存器位于包括在硬件加速器单元内的电路内。 该方法还可以包括从微引擎向具有该电路的硬件加速器单元发出命令集。 该方法可以另外包括接收来自微引擎的电路处的命令集，该命令集被配置为允许处理各种不同的操作。 该方法还可以包括基于加载到硬件配置寄存器中的配置数据来处理适当的操作。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US07953221B2

公开(公告)日：2011-05-31

申请号：US11617418

申请日：2006-12-28

申请人： Wajdi Feghali ,  Stephanie Hirnak ,  Makaram Raghunandan ,  Yogesh Bansal ,  Kirk Yap ,  Gilbert M. Wolrich

发明人： Wajdi Feghali ,  Stephanie Hirnak ,  Makaram Raghunandan ,  Yogesh Bansal ,  Kirk Yap ,  Gilbert M. Wolrich

IPC分类号： H04K1/00 ,  H04K1/04 ,  H04K1/06 ,  H04L9/00 ,  H04L9/28 ,  H04L9/32

CPC分类号： H04L63/0485 ,  G06F9/30181 ,  G06F9/3879 ,  H04L63/08

摘要： In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 在一个实施例中，本公开提供了一种能够处理各种不同操作的方法。 根据一个实施例的方法可以包括将配置数据从共享存储器单元加载到硬件配置寄存器中，硬件配置寄存器位于包括在硬件加速器单元内的电路内。 该方法还可以包括从微引擎向具有该电路的硬件加速器单元发出命令集。 该方法可以另外包括接收来自微引擎的电路处的命令集，该命令集被配置为允许处理各种不同的操作。 该方法还可以包括基于加载到硬件配置寄存器中的配置数据来处理适当的操作。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20100153829A1

公开(公告)日：2010-06-17

申请号：US12336029

申请日：2008-12-16

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

IPC分类号： H03M13/09 ,  G06F7/72 ,  G06F11/10

CPC分类号： G06F7/724 ,  H03M13/091

摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

摘要翻译： 在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。 操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少 是乘法的结果。 所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值 另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。

公开(公告)号：US08042025B2

公开(公告)日：2011-10-18

申请号：US12291621

申请日：2008-11-12

申请人： Vinodh Gopal ,  Gilbert Wolrich ,  Wajdi Feghali ,  Erdinc Ozturk ,  Shay Gueron

发明人： Vinodh Gopal ,  Gilbert Wolrich ,  Wajdi Feghali ,  Erdinc Ozturk ,  Shay Gueron

IPC分类号： H03M13/03

CPC分类号： G06F7/724 ,  H03M13/091

摘要： In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.

摘要翻译： 在一个方面，用于确定相对于包括一系列段的消息的多项式的模块余数的电路。 在另一方面，访问具有第一末端格式的第一号码的至少一部分的电路基于具有与第一末端格式相反的端格式的第三号码的位反射和位移来确定第二号码，以及 执行第一数字和第一数字的至少一部分的多项式相乘。