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    Floating Point Intensive Reconfigurable Computing System for Iterative Applications
    1.
    发明申请
    Floating Point Intensive Reconfigurable Computing System for Iterative Applications 审中-公开
    浮点密集可重构计算系统的迭代应用

    公开(公告)号：US20070067380A2

    公开(公告)日：2007-03-22

    申请号：US10862269

    申请日：2004-06-07

    申请人： Brian Bishop ,  Thomas Kelliher ,  Shrirang Yardi

    发明人： Brian Bishop ,  Thomas Kelliher ,  Shrirang Yardi

    IPC分类号： G06F15/00

    CPC分类号： G06F9/3885 ,  G06F9/3887 ,  G06F15/8023

    摘要： A reconfigurable computing system for accelerating execution of floating point intensive iterative applications. The reconfigurable computing system includes a plurality of interconnected processing elements mounted on a printed circuit board, a host processing system for displaying real-time outputs of the floating point calculations performed by the processing elements, and an interface for connecting the processing elements to the host system. Each of the interconnected processing elements includes a floating point functional unit, operand memory, control memory and a control unit. The floating point functional unit includes a multiply accumulate function. The operand memory includes a plurality of banks of static random access memory. The processing elements are interconnected using a nearest neighbor or hierarchical implementation. The instruction set performed by the floating point functional unit includes arithmetic, control and communication instructions. The interface can be implemented as a PCI bus interface using a field programmable gate array or as an AGP bus interface.

    摘要翻译： 用于加速浮点密集迭代应用程序执行的可重构计算系统。 可重构计算系统包括安装在印刷电路板上的多个互连的处理元件，用于显示由处理元件执行的浮点计算的实时输出的主处理系统，以及用于将处理元件连接到主机 系统。 每个互连的处理元件包括浮点功能单元，操作数存储器，控制存储器和控制单元。 浮点功能单元包括乘法累加函数。 操作数存储器包括多个静态随机存取存储器组。 处理元件使用最近邻或分层实现互连。 由浮点功能单元执行的指令集包括算术，控制和通信指令。 该接口可以实现为使用现场可编程门阵列或AGP总线接口的PCI总线接口。