公开(公告)号：US20060236032A1

公开(公告)日：2006-10-19

申请号：US11105265

申请日：2005-04-13

申请人： Brian Campbell ,  Brian Magnuson ,  Ofer Porat ,  David Scheffey ,  Clayton Curry

发明人： Brian Campbell ,  Brian Magnuson ,  Ofer Porat ,  David Scheffey ,  Clayton Curry

IPC分类号： G06F12/00

CPC分类号： G06F12/0866 ,  G06F2212/261

摘要： A memory system includes a bank of memory, an interface to a packet switching network, and a memory controller. The memory system is adapted to receive by the interface a packet based command to access the bank of memory. The memory controller is adapted to execute initialization and configuration cycles for the bank of memory. An embedded central processing unit (CPU) is included in the memory controller and is adapted to execute computer executable instructions. The memory controller is adapted to process the packet based command.

摘要翻译： 存储器系统包括一组存储器，到分组交换网络的接口和存储器控制器。 存储器系统适于由接口接收基于分组的命令来访问存储器组。 存储器控制器适于对存储器组执行初始化和配置周期。 嵌入式中央处理单元（CPU）包括在存储器控制器中并且适于执行计算机可执行指令。 存储器控制器适于处理基于分组的命令。