Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
    1.
    发明授权
    Semiconductor device having optimized shallow junction geometries and method for fabrication thereof 有权
    具有优化的浅结几何形状的半导体器件及其制造方法

    公开(公告)号:US07098099B1

    公开(公告)日:2006-08-29

    申请号:US11064583

    申请日:2005-02-24

    IPC分类号: H01L21/8238

    摘要: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.

    摘要翻译: 本发明在一个实施例中提供一种制造半导体器件(100)的方法。 在一个实施例中,该方法包括在第一掺杂剂区域122和第二掺杂剂区域128之上从衬底104,106生长氧化物层120,将第一掺杂剂注入到氧化物层120中,将第一掺杂剂注入第一掺杂剂区域 并且与栅极结构114相邻,并且在第二掺杂剂区域128内基本上从衬底去除氧化物层120。 在第二掺杂区域128中除去氧化物层120之后,将与第一掺杂剂类型相反的第二掺杂剂注入到衬底106中并且在第二掺杂剂区域128内并且与栅极结构114相邻。

    Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
    2.
    发明授权
    Semiconductor device having optimized shallow junction geometries and method for fabrication thereof 有权
    具有优化的浅结几何形状的半导体器件及其制造方法

    公开(公告)号:US07033879B2

    公开(公告)日:2006-04-25

    申请号:US10835121

    申请日:2004-04-29

    IPC分类号: H01L21/8238 H01L21/336

    摘要: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).

    摘要翻译: 本发明在一个实施例中提供一种制造半导体器件(100)的方法。 该方法包括在栅极结构(114)和衬底(102)上生长氧化物层(120)并将掺杂剂(124)注入到衬底(102)和氧化物层(120)中。 注入使得掺杂剂(124)的一部分保留在氧化物层(120)中以形成注入的氧化物层(126)。 该方法还包括在注入的氧化物层(126)上沉积保护性氧化物层(132)并且形成耐腐蚀的偏置间隔物(134)。 在栅极结构(114)的侧壁和保护氧化物层(132)上形成耐蚀刻偏置间隔物(134)。 耐腐蚀的偏置间隔件具有邻近侧壁的内周边(135)和相对的外周边(136)。 该方法还包括去除位于耐蚀刻偏移间隔物(134)的外周(136)外的保护氧化物层(132)的部分。 本发明的其他实施例包括晶体管器件(200)和制造集成电路(300)的方法。