Method to reduce contact resistance on thin silicon-on-insulator device
    1.
    发明授权
    Method to reduce contact resistance on thin silicon-on-insulator device 失效
    降低绝缘体上硅器件接触电阻的方法

    公开(公告)号:US07479437B2

    公开(公告)日:2009-01-20

    申请号:US11413010

    申请日:2006-04-28

    IPC分类号: H01L21/336

    摘要: A method of reducing contact resistance on a silicon-on-insulator includes exposing sidewalls and a portion of a top surface of a source/drain region of the device, forming a porous silicon layer within a surface of the source/drain region, implanting dopants in the source/drain region, and forming a silicide layer over the source/drain region. The porous silicon layer is formed by forming a layer of p+ doping on the exposed sidewalls and portion of the top surface of the source/drain region, forming a nitride liner over the device, including the source/drain region and the layer of p+ doping, forming a planarized resist over the nitride liner, recessing the planarized resist and etching the nitride liner to expose portions of the source/drain region, and forming the porous silicon layer on the exposed portions of the source drain region.

    摘要翻译: 降低绝缘体上硅的接触电阻的方法包括暴露该器件源极/漏极区的侧壁和一部分上表面,在源/漏区的表面内形成多孔硅层,注入掺杂剂 在源极/漏极区域中,并且在源极/漏极区域上形成硅化物层。 通过在暴露的源极/漏极区域的顶表面的侧壁和部分上形成p +掺杂层形成多孔硅层,在器件上形成氮化物衬垫,包括源/漏区和p +掺杂层 在所述氮化物衬垫上形成平坦化的抗蚀剂,使所述平坦化抗蚀剂凹陷并蚀刻所述氮化物衬垫以暴露所述源/漏区的部分,以及在所述源漏区的所述暴露部分上形成所述多孔硅层。