公开(公告)号：US10031994B1

公开(公告)日：2018-07-24

申请号：US15219008

申请日：2016-07-25

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Wen Hao Liu ,  Jhih-Rong Gao ,  Mehmet Yildiz ,  Charles Alpert ,  Zhuo Li

IPC: G06F17/50

Abstract: Disclosed herein are systems and methods to reduce wirelength and congestion in an integrated circuit (IC) design. The systems and methods disclosed herein may be implemented during a detailed placement stage of IC design to identify and select a cell for relocation and determine an area of interest to which the cell can be relocated. The systems and methods may identify one or more potential locations within the area of interest where the cell can be relocated to, and then determine a cost based upon the wirelength and/or congestion for the selected cell, at each of the one or more potential locations. Upon determining that a potential location may have a lower cost compared to the original location of the selected cell, the systems and methods may relocate the selected cell to the potential location.

公开(公告)号：US10095824B1

公开(公告)日：2018-10-09

申请号：US15293010

申请日：2016-10-13

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Zhuo Li ,  Wen-Hao Liu ,  Charles Alpert ,  Brian Wilson

IPC: G06F17/00 ,  G06F17/50

Abstract: Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such symmetrically balanced clock-tree ensures that a clock-signal reaches all of the clock-sinks simultaneously or near simultaneously thereby minimizing clock-skew across the clock-sinks. The minimal skew symmetric clock-distribution H-tree may therefore be used for higher performance and high speed ICs.

公开(公告)号：US10216880B1

公开(公告)日：2019-02-26

申请号：US15212002

申请日：2016-07-15

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Wen-Hao Liu ,  Zhuo Li ,  Charles Alpert ,  Brian Wilson

IPC: G06F17/50

Abstract: Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a load-balancing process. In another embodiment, the methods use a local cleanup process to rewire the nodes between neighboring clock buffers to further reduce the amount of clock-gaters.