公开(公告)号：US09928328B1

公开(公告)日：2018-03-27

申请号：US15164514

申请日：2016-05-25

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Ynon Cohen ,  Tal Tabakman ,  Yonatan Ashkenazi ,  Chung-Wah Norris IP ,  Nadav Chazan ,  Gavriel Leshem

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/505

Abstract: A method for automated debugging of a design under test (DUT), including using a processor, (a) identifying a value of a signal at a specific time instance in which a user has indicated interest; (b) performing driver tracing based on structural analysis and signal analysis to determine one or a plurality of drivers of the identified value in the signal; (c) if the driver tracing returns a single driver of said one or a plurality of drivers, presenting the returned single driver to the user via an output device; and (d) if the driver tracing returns a plurality of drivers of said one or a plurality of drivers, performing formal analysis on a compiled sub-structure of the DUT to which all of said returned plurality of drivers are related to determine a single driver from said returned plurality of drivers, and presenting the determined single driver from said returned plurality of drivers to the user via the output device.