公开(公告)号：US10521543B1

公开(公告)日：2019-12-31

申请号：US15642848

申请日：2017-07-06

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Laurent Saint-Marcel

IPC: G06F17/50 ,  G06F16/532

Abstract: Disclosed herein are embodiments of systems, methods, and products for dynamically determining and rendering a target resistance of a partially routed net between two circuit devices in an integrated circuit (IC) design and automatically resizing a wire segment being edited in real time based on the target resistance such that the fully routed net satisfies the maximum resistance constraint. Therefore, the embodiments disclosed herein simplify the circuit designer's job and improves design productivity. Unlike conventional systems, an EDA tool disclosed herein does not have to route the full net between two circuit devices to run design rule checking (DRC). Thus, the EDA tool does not require multiple iterations of fully routing a net and checking for DRC violations such that the maximum resistance constraint is not violated.