公开(公告)号：US11531550B2

公开(公告)日：2022-12-20

申请号：US17173067

申请日：2021-02-10

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Christopher Olson

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48

Abstract: Techniques are disclosed relating to an apparatus that includes a plurality of execution pipelines including first and second execution pipelines, a shared circuit that is shared by the first and second execution pipelines, and a decode circuit. The first and second execution pipelines are configured to concurrently perform operations for respective instructions. The decode circuit is configured to assign a first program thread to the first execution pipeline and a second program thread to the second execution pipeline. In response to determining that respective instructions from the first and second program threads that utilize the shared circuit are concurrently available for dispatch, the decode circuit is further configured to select between the first program thread and the second program thread.