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公开(公告)号：US12287369B1
公开(公告)日：2025-04-29
申请号：US18364064
申请日：2023-08-02
Applicant: Cadence Design Systems, Inc.
Inventor： Patrick Murphy , Cornelius O'Shea , Joe Canning , Dariusz Piotr Palubiak , Vitali Karasenko
IPC: G01R31/3185
Abstract: Embodiments include herein are directed towards various circuit topologies. A self-correcting latch circuit may include a plurality of memory loops, a plurality of clock inputs, a plurality of data inputs, and a plurality of outputs. Each of the plurality of memory loops may be configured to store data in parallel.
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