公开(公告)号：US11501049B1

公开(公告)日：2022-11-15

申请号：US16145561

申请日：2018-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Feng Miao ,  Jing Wang ,  Zhen Mu ,  Xuegang Zeng

IPC: G06F30/367 ,  G06F113/20

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include performing, using a processor, a simulation of a multi-layered electronic structure and extracting a circuit model of the multi-layered electronic structure, wherein the circuit model includes at least two plates. Embodiments may also include extracting one or more parasitic parameters of at least one via associated with the circuit model and calculating a coupling coefficient associated with a controlled source of the circuit model. Embodiments may further include extracting a transmission line mode from the circuit model and linking the circuit model, at least one via, and the transmission line mode to an external circuit to generate a modeled system. Embodiments may also include solving the modeled system using a modified nodal analysis.