公开(公告)号：US10482211B1

公开(公告)日：2019-11-19

申请号：US15886119

申请日：2018-02-01

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Laurent Rene Saint-Marcel ,  Laurent Robert Chouraki ,  Alexandre Roger Maurice Soyer

IPC: G06F17/50 ,  G06F3/0484

Abstract: In an electronic circuit design system, a physical layout of at least part of an electronic circuit design is visually rendered. Magnitude of current loading are determined at one or more of the circuit nodes, or one or more clusters of nodes grouped according to predetermined clustering criteria, for a selected net or nets. The range of magnitudes is mapped to at least one gradation range for visual indicia of preselected type, such as a predetermined color spectrum; preferably, alternative gradation ranges respectively for current sources and current sinks are provided. The visual indicia of the current loading magnitudes are then adaptively displayed to overlay the corresponding circuit nodes or clusters in the rendered physical layout, providing a reference for a designer to proportionately size segments of the selected net or nets, as well as spacing required for the segments.

公开(公告)号：US11373027B1

公开(公告)日：2022-06-28

申请号：US17194589

申请日：2021-03-08

Applicant: Cadence Design Systems, Inc.

Inventor： Laurent Rene Saint-Marcel

IPC: G06F30/394 ,  G06F30/12

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, at a graphical user interface, an indication of a desired wire creation associated with an electronic design and determining a plurality of routing solutions, based upon, at least in part, the desired wire creation. Embodiments may further include simultaneously displaying the plurality of routing solutions at the graphical user interface, wherein a predicted preferred routing solution is graphically emphasized. Embodiments may also include receiving a selection from a user, at the graphical user interface, of one of the plurality of routing solutions and storing the selection for subsequent use.

公开(公告)号：US10380314B1

公开(公告)日：2019-08-13

申请号：US15591548

申请日：2017-05-10

Applicant: Cadence Design Systems, Inc.

Inventor： Laurent Rene Saint-Marcel

IPC: G06F17/50

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, the electronic design and identifying a partially routed net associated with the electronic design. Embodiments may further include generating a net graph for the partially routed net and selecting a wire associated with the partially routed net. Embodiments may also include determining a missing current needed to satisfy Kirchhoff's Current Law (“KCL”) along a portion of the wire and generating a virtual terminal attached to the selected wire, wherein the virtual terminal is assigned the missing current.