公开(公告)号：US10108767B1

公开(公告)日：2018-10-23

申请号：US15282627

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Victor Markus Purri ,  Michael Dennis Pedneau ,  Lars Lundgren ,  Pradeep Goyal

IPC: G06F17/50

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing deadlock detection with formal verification techniques in an electronic design. These techniques identify one or more inputs that include at least an initial state of an electronic design and identify at least one deadlock candidate by sweeping at least a portion of a state space of the electronic design with formal verification techniques. These techniques then determine whether the at least one deadlock candidate is a real deadlock by using a second formal search with the formal verification techniques.