公开(公告)号：US09501590B1

公开(公告)日：2016-11-22

申请号：US14639014

申请日：2015-03-04

Applicant: Cadence Design Systems, Inc.

Inventor： Paul A. Cunningham ,  Steev Wilcox ,  Vivek Chickermane

IPC: G06F17/50

CPC classification number: G01R31/31704 ,  G01R31/318583

Abstract: A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.

公开(公告)号：US09465896B1

公开(公告)日：2016-10-11

申请号：US14639029

申请日：2015-03-04

Applicant: Cadence Design Systems, Inc.

Inventor： Paul A. Cunningham ,  Steev Wilcox ,  Vivek Chickermane

IPC: G06F17/50

CPC classification number: G01R31/44 ,  G01R31/28 ,  G06F17/5045 ,  G06F2217/14

Abstract: A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.

Abstract translation: CoDec在设计中用于测试集成电路。 在本文描述的实施例中，CoDec的部分分布在IC的区域上。 特别地，压缩机和解压缩器都可以分布在IC上。 为此，XOR栅极位于芯片区域上的扫描链的本地，以将电线长度减小到输入/输出测试引脚。 压缩机和解压缩器可以分布在二维网格中。 压缩器可以在两个不同的方向上对每个扫描链进行异或，使得故障可以被解回到IC的特定区域。