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1.发明授权公开(公告)号：US11574111B1
公开(公告)日：2023-02-07
申请号：US17139876
申请日：2020-12-31
Applicant: Cadence Design Systems, Inc.
Inventor： Rwik Sengupta , Jeffrey Nelson , Philippe Hurat , Jac Paul P. Condella
IPC: G06F30/398 , G06F16/532
Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing an approach to facilitate traceability and tamper detection of electronic designs. This approach allows for tracing and tamper detection at any stage of design and manufacturing, such as during layout generation, post-design, post-mask, and post manufacturing of the electronic designs.
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