公开(公告)号：US08595681B1

公开(公告)日：2013-11-26

申请号：US13717419

申请日：2012-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Senthil Arasu Thirunavukarasu ,  Shaleen Bhabu ,  Vivek Chickermane

IPC: G06F17/50

CPC classification number: G01R31/318533

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.