公开(公告)号：US10540461B1

公开(公告)日：2020-01-21

申请号：US16038152

申请日：2018-07-17

Applicant: Cadence Design Systems, Inc.

Inventor： Shai Mizrachi ,  Eyal Gvili

IPC: G06F17/50 ,  G06K9/62 ,  G06F16/901

Abstract: A method for functional safety verification for use in a verification of a design under test (DUT), includes obtaining a set of verification tests previously executed on the DUT and related execution data; injecting a fault into each of the tests of the set of verification tests; analyzing a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree; and for each of the clusters of faults, based on the execution data, performing test ordering of tests from the set of verification tests according to likelihood of classifying the faults under the child node in which that cluster is located.