公开(公告)号：US09379846B1

公开(公告)日：2016-06-28

申请号：US14578173

申请日：2014-12-19

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell G. Poplack ,  Simon Sabato

IPC: H03M13/00 ,  H04L1/00 ,  G06F11/10

CPC classification number: H04L1/0041 ,  G06F11/10 ,  H04L1/0071

Abstract: In one form a method of encoding a data word for serial transmission is provided, where a data word comprising a plurality of data bits is received, an invert bit having a bit value is appended to the data word, the data bits and invert bit are scrambled, ECC check bits are generated, and the data bits, invert bit, and ECC check bits are shuffled together to form an encoded word to be transmitted from a transmitter. A receiver may decode by implementing a decode process with error correction. The encoded word may also be DC balanced by checking the disparity of the bits to be encoded against a running disparity to invert or not the bits. An integrated circuit serializer/deserializer comprises hardware to perform encoding and/or decoding. A hardware functional verification system may implement the disclosed encoding/decoding for interconnections between emulation chips.

Abstract translation: 提供一种编码用于串行传输的数据字的方法，其中接收包括多个数据位的数据字，将具有位值的反转比特附加到数据字，数据位和反转位是 生成ECC校验位，并将数据位，反转位和ECC校验位混合在一起形成要从发送器发送的编码字。 接收机可以通过实施具有纠错的解码过程进行解码。 编码的字也可以通过根据运行的差异检查待编码的比特的差异来反转或不转换比特来进行直流平衡。 集成电路串行器/解串器包括执行编码和/或解码的硬件。 硬件功能验证系统可以实现所公开的编码/解码以用于仿真芯片之间的互连。

公开(公告)号：US09647688B1

公开(公告)日：2017-05-09

申请号：US14578100

申请日：2014-12-19

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell G. Poplack ,  Simon Sabato

IPC: H03M13/00 ,  H03M13/03

CPC classification number: H03M13/03 ,  H03M13/31

Abstract: A method of encoding a data word in a physical coding sublayer before serial transmission is provided, where data words comprising data bits are received, and the data words encoded using one or more 8B/10B encodings to generate 8B/10B transmission characters. ECC check bits are then generated, and the transmission characters and ECC check bits DC balanced prior to shuffling the bits together to form an encoded word to be transmitted. A receiver may decode by implementing a decode process with error correction. In some embodiments 26 data bits from two 13-bit word are encoded into a 40-bit encoded word. Bits of two or more encoded words may be interleaved for transmission, or multiple copies of encoded words sent. An integrated circuit serializer/deserializer comprises hardware to perform encoding and/or decoding. A hardware functional verification system may also implement the disclosed encoding/decoding for interconnections between emulation chips.