公开(公告)号：US11630938B1

公开(公告)日：2023-04-18

申请号：US16673792

申请日：2019-11-04

Applicant: Cadence Design Systems, Inc.

Inventor： Stefano Lorenzini ,  Antonino Armato

IPC: G06F30/398 ,  G06F11/07 ,  G05B23/02 ,  G06F11/00 ,  G06F30/394 ,  G06F11/26

Abstract: Various embodiments provide for failure mode analysis of a circuit design, which can be used as part of electronic design automation (EDA). In particular, some embodiments provide for failure mode analysis of a circuit design by determining a set of functional primitives of a circuit design component (e.g., cell at gate level) that contribute to a root cause logic for a specific failure mode.