公开(公告)号：US20080134110A1

公开(公告)日：2008-06-05

申请号：US12015631

申请日：2008-01-17

申请人： Chaitra M. Bhat ,  M. Chandrika ,  Atsushi Sugai ,  Toshihiko Yokota

发明人： Chaitra M. Bhat ,  M. Chandrika ,  Atsushi Sugai ,  Toshihiko Yokota

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.

公开(公告)号：US07356797B2

公开(公告)日：2008-04-08

申请号：US11153707

申请日：2005-06-14

申请人： Chaitra M. Bhat ,  M. Chandrika ,  Atsushi Sugai ,  Toshihiko Yokota

发明人： Chaitra M. Bhat ,  M. Chandrika ,  Atsushi Sugai ,  Toshihiko Yokota

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.

摘要翻译： 一种避免布线堵塞的新颖逻辑设计方法。 根据新颖的逻辑设计方法，可以将具有来自不同方向的多个输入并且具有进入不同方向的多个输出的原始门转换为具有输入级和输出级的逻辑块。 输入级的门从原始门的多个输入接收信号。 输出级的门将信号发送到原始门的多个输出。 输入级的每个门都放置在其输入端附近。 输出级的每个门都放置在其输出端附近。 输入和输出级的门在功能上等同于原始门。

公开(公告)号：US08006210B2

公开(公告)日：2011-08-23

申请号：US12014344

申请日：2008-01-15

申请人： Chaitra M. Bhat ,  Chandrika Madhwacharya ,  Atsushi Sugai ,  Toshihiko Yokota

发明人： Chaitra M. Bhat ,  Chandrika Madhwacharya ,  Atsushi Sugai ,  Toshihiko Yokota

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.

摘要翻译： 一种避免布线堵塞的新颖逻辑设计方法。 根据新颖的逻辑设计方法，可以将具有来自不同方向的多个输入并且具有进入不同方向的多个输出的原始门转换为具有输入级和输出级的逻辑块。 输入级的门从原始门的多个输入接收信号。 输出级的门将信号发送到原始门的多个输出。 输入级的每个门都放置在其输入端附近。 输出级的每个门都放置在其输出端附近。 输入和输出级的门在功能上等同于原始门。

公开(公告)号：US08161445B2

公开(公告)日：2012-04-17

申请号：US12015631

申请日：2008-01-17

申请人： Chaitra M. Bhat ,  Chandrika Madhwacharya ,  Atsushi Sugai ,  Toshihiko Yokota

发明人： Chaitra M. Bhat ,  Chandrika Madhwacharya ,  Atsushi Sugai ,  Toshihiko Yokota

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.

摘要翻译： 一种避免布线堵塞的新颖逻辑设计方法。 根据新颖的逻辑设计方法，可以将具有来自不同方向的多个输入并且具有进入不同方向的多个输出的原始门转换为具有输入级和输出级的逻辑块。 输入级的门从原始门的多个输入接收信号。 输出级的门将信号发送到原始门的多个输出。 输入级的每个门都放置在其输入端附近。 输出级的每个门都放置在其输出端附近。 输入和输出级的门在功能上等同于原始门。