公开(公告)号：US20050138578A1

公开(公告)日：2005-06-23

申请号：US10738711

申请日：2003-12-17

申请人： Charles Alpert ,  Rama Gandham ,  Milos Hrkic ,  Stephen Quay

发明人： Charles Alpert ,  Rama Gandham ,  Milos Hrkic ,  Stephen Quay

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/505

摘要： A mechanism for constructing Steiner trees using simultaneous blockage avoidance, delay optimization, and design density management are provided. An initial tiled timing-driven Steiner tree is obtained for an integrated circuit design. The Steiner tree is broken into 2-paths for which plates are generated designated the permissible area in which a Steiner point may migrate. Each 2-path is optimized by calculating a cost for each tile in the plate as a function of an environmental cost, a tile delay cost, and a trade-off value. A minimum cost tile is then selected as the point to which the Steiner point in the 2-path, if any, is to migrate. Once each 2-path is processed in this manner, routing is performed so as to minimize the cost at the source. This process may be iteratively repeated with new trade-off values until all of the nets have zero or positive slew.

摘要翻译： 提供了一种使用同时阻止避免，延迟优化和设计密度管理构建Steiner树的机制。 获得用于集成电路设计的初始平铺时序驱动的Steiner树。 Steiner树被分解为2路径，其中生成了板，指定Steiner点可能迁移的允许区域。 通过根据环境成本，瓦片延迟成本和折衷值计算板中每个瓦片的成本来优化每个2路径。 然后选择最小成本图块作为2路径中Steiner点（如果有）要迁移的点。 一旦以这种方式处理了每个2路径，就执行路由以最小化源的成本。 可以用新的权衡值迭代地重复该过程，直到所有网络具有零或正的摆动。

公开(公告)号：US20050151258A1

公开(公告)日：2005-07-14

申请号：US10755590

申请日：2004-01-12

申请人： Pooja Kotecha ,  Rama Gandham ,  Ruchir Puri ,  Louise Trevillyan ,  Adam Matheny

发明人： Pooja Kotecha ,  Rama Gandham ,  Ruchir Puri ,  Louise Trevillyan ,  Adam Matheny

IPC分类号： G06F17/50 ,  H01L23/52 ,  H01L29/40

CPC分类号： G06F17/5077

摘要： A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.