公开(公告)号：US08386985B2

公开(公告)日：2013-02-26

申请号：US13102776

申请日：2011-05-06

申请人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay ,  Ying Zhou

发明人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay ,  Ying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5077 ,  G06F2217/84

摘要： A method, system, and computer program product for timing driven routing in a design of an integrated circuit (IC) are provided in the illustrative embodiments. A router application executing in a data processing system performs a pre-global routing optimization of the design. A plurality of wirelength target constraints are set on a plurality of subsets of a set of nets in the design. Global routing is performed on the design. The design is adjusted using wires placed in the design during the global routing. A priority is assigned to each net in the set of nets. Detailed routing is performed on the design.

摘要翻译： 在说明性实施例中提供了用于在集成电路（IC）的设计中的定时驱动路由的方法，系统和计算机程序产品。 在数据处理系统中执行的路由器应用程序执行设计的全局前路由优化。 在设计中的一组网络的多个子集上设置多个线长目标约束。 在设计上执行全局路由。 在全局路由期间，使用设计中的电线来调整设计。 优先级分配给网络集合中的每个网络。 在设计上执行详细的路由。

公开(公告)号：US20120284683A1

公开(公告)日：2012-11-08

申请号：US13102776

申请日：2011-05-06

申请人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay ,  Ying Zhou

发明人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay ,  Ying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5077 ,  G06F2217/84

摘要： A method, system, and computer program product for timing driven routing in a design of an integrated circuit (IC) are provided in the illustrative embodiments. A router application executing in a data processing system performs a pre-global routing optimization of the design. A plurality of wirelength target constraints are set on a plurality of subsets of a set of nets in the design. Global routing is performed on the design. The design is adjusted using wires placed in the design during the global routing. A priority is assigned to each net in the set of nets. Detailed routing is performed on the design.

摘要翻译： 在说明性实施例中提供了用于在集成电路（IC）的设计中的定时驱动路由的方法，系统和计算机程序产品。 在数据处理系统中执行的路由器应用程序执行设计的全局前路由优化。 在设计中的一组网络的多个子集上设置多个线长目标约束。 在设计上执行全局路由。 在全局路由期间，使用设计中的电线来调整设计。 优先级分配给网络集合中的每个网络。 在设计上执行详细的路由。

公开(公告)号：US07392493B2

公开(公告)日：2008-06-24

申请号：US10996292

申请日：2004-11-22

申请人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

发明人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from any buffered node to any sink less than a required slew rate. The slew analysis computes an output slew SL(v) of a given buffer b inserted at a node v as SL(v)=RS(b)·C(v)+KS(b), where C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b. The delay through a given buffer may also be computed based on signal polarity. However, the invention still preferably uses worst-case slew resistance and intrinsic slew in considering the slew constraints. If the selection of the buffer insertion locations results in no locations being selected due to slew violations, the present invention may advantageously find a partial solution by relaxing the slew constraint.

摘要翻译： 在集成电路设计中确定缓冲器插入位置的方法建立了用于将缓冲器插入网络的候选位置，并且基于回转约束从候选中选择缓冲器插入位置。 缓冲器插入位置的选择优选地优化松弛和缓冲器成本，同时保持从任何缓冲节点转到任何小于所需转换速率的接收端。 滑动分析计算插入在节点v处的给定缓冲器b的输出滑动SL（v）为SL（v）= RS（b）.C（v）+ KS（b），其中C（v）是下游 电容在v，RS（b）是缓冲器b的耐压，KS（b）是缓冲器b的固有电压。 也可以基于信号极性来计算给定缓冲器的延迟。 然而，本发明在考虑压摆约束的情况下仍然优选地使用最坏情况的耐回转电阻和固有的电压。 如果缓冲器插入位置的选择导致没有被选择的位置，因为本发明可以通过放松压摆约束来有利地找到部分解决方案。

公开(公告)号：US07676780B2

公开(公告)日：2010-03-09

申请号：US11947706

申请日：2007-11-29

申请人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

发明人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from any buffered node to any sink less than a required slew rate. The slew analysis computes an output slew SL(v) of a given buffer b inserted at a node v as SL(v)=RS(b)·C(v)+KS(b), where C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b. The delay through a given buffer may also be computed based on signal polarity. However, the invention still preferably uses worst-case slew resistance and intrinsic slew in considering the slew constraints. If the selection of the buffer insertion locations results in no locations being selected due to slew violations, the present invention may advantageously find a partial solution by relaxing the slew constraint.

摘要翻译： 在集成电路设计中确定缓冲器插入位置的方法建立了用于将缓冲器插入网络的候选位置，并且基于回转约束从候选中选择缓冲器插入位置。 缓冲器插入位置的选择优选地优化松弛和缓冲器成本，同时保持从任何缓冲节点转到任何小于所需转换速率的接收端。 转换分析计算插入节点v的给定缓冲器b的输出转换SL（v）为SL（v）= RS（b）·C（v）+ KS（b），其中C（v）是下游 电容在v，RS（b）是缓冲器b的耐压，KS（b）是缓冲器b的固有电压。 也可以基于信号极性来计算给定缓冲器的延迟。 然而，本发明在考虑压摆约束的情况下仍然优选地使用最坏情况的耐回转电阻和固有的电压。 如果缓冲器插入位置的选择导致没有被选择的位置，因为本发明可以通过放松压摆约束来有利地找到部分解决方案。

公开(公告)号：US07299442B2

公开(公告)日：2007-11-20

申请号：US11032878

申请日：2005-01-11

申请人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

发明人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method of estimating routing congestion between pins in a net of an integrated circuit design, by establishing one or more potential routes between the pins which pass through buckets in the net, assigning a probabilistic usage to each bucket based on any partial blockage of the wiring tracks in each bucket, and computing routing congestion for each bucket using its probabilistic usage. When the net is a two-pin net that is a part of a larger multi-pin net, and a tree is constructed to bridge the two-pin net to another pin of the multi-pin net. The routing congestion for each bucket is computed as a ratio of the bucket usage to bucket capacity. For L-shaped routes (having at least one bend in a bucket), the probabilistic usage is proportional to a scale factor a which is a ratio of a minimum number of available wiring tracks for a given route to a sum of minimum numbers of available wiring tracks for all possible routes. For Z-shaped routes (having at least two bends in two respective buckets), the probabilistic usage is equal to a ratio of a minimum capacity of a given route to a sum of minimum capacities of all routes having an associated orientation with the given route. Assignment of the usage values may entail the creation of a temporary usage map of the net buckets with an initial value of zero usage in every temporary usage map bucket, thereafter storing usage values in corresponding buckets of the temporary usage map, and deriving a final usage map from the temporary usage map.

摘要翻译： 一种在集成电路设计的网络中估计引脚之间的路由拥塞的方法，通过在通过网络中的网段的引脚之间建立一个或多个潜在路由，基于线路的任何部分阻塞向每个分组分配概率使用 每个桶中的轨道，以及使用其概率使用来计算每个桶的路由拥塞。 当网是作为较大多针网的一部分的双引脚网络，并且构造一棵树将双引脚网络桥接到多引脚网的另一个引脚。 每个桶的路由拥塞被计算为桶使用量与桶容量的比率。 对于L形路径（在桶中至少有一个弯道），概率使用与比例因子a成比例，比例因子a是给定路线的可用线路的最小数量与可用的最小数量之和的比率 所有可能的路线的线路。 对于Z形路线（在两个相应的桶中具有至少两个弯曲），概率使用等于给定路由的最小容量与具有与给定路由相关联的定向的所有路由的最小容量之和的比率 。 使用值的分配可能需要在每个临时使用地图桶中创建具有零使用的初始值的网络桶的临时使用图，然后将使用值存储在临时使用映射的相应桶中，并且导出最终使用 从临时使用地图映射。

公开(公告)号：US08656334B2

公开(公告)日：2014-02-18

申请号：US12832180

申请日：2010-07-08

申请人： Charles Jay Alpert ,  Zhuo Li ,  Arjen Alexander Mets ,  Ying Zhou

发明人： Charles Jay Alpert ,  Zhuo Li ,  Arjen Alexander Mets ,  Ying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/08

摘要： A method, system, and computer usable program product for multiple threshold voltage cell families (mVt families) based integrated circuit design are provided in the illustrative embodiments. The integrated circuit includes cells, and a cell includes an electronic component. A design process is initialized by using cells from the mVt families in the design. The cells from the mVt families are included in iterative manipulation of the design. The cells from the mVt families are further included in violation cleanup and subsequent steps of the design process. A version of the design is produced that is usable to implement the circuit with the cells from the mVt families.

摘要翻译： 在说明性实施例中提供了用于多个阈值电压单元族（mVt系列）的集成电路设计的方法，系统和计算机可用程序产品。 集成电路包括单元，单元包括电子元件。 通过使用设计中的mVt系列的单元格初始化设计过程。 来自mVt系列的单元格被包含在设计的迭代操作中。 来自mVt系列的单元格进一步包含在违规清理和设计过程的后续步骤中。 产生了一种可用于使用来自mVt系列的单元实现电路的设计版本。

公开(公告)号：US08677305B2

公开(公告)日：2014-03-18

申请号：US13488065

申请日：2012-06-04

申请人： Charles Jay Alpert ,  Joseph Nicolas Kozhaya ,  Zhuo Li ,  Joseph J Palumbo ,  Haifeng Qian ,  Phillip John Restle ,  Chin Ngai Sze ,  Ying Zhou

发明人： Charles Jay Alpert ,  Joseph Nicolas Kozhaya ,  Zhuo Li ,  Joseph J Palumbo ,  Haifeng Qian ,  Phillip John Restle ,  Chin Ngai Sze ,  Ying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/62

摘要： An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.

摘要翻译： 具有接收器定位器单元的电子自动化设计工具基于平衡负载集群中的负载的大小并且基于每个集群的最小延迟，从时钟网络设计的扇区内的多个负载中产生负载集群，以及 在时钟网络设计的扇区中的多个接收器位置中的相应的一个。 该工具确定负载集群的中心，并确定与簇的中心对应的接收位置，以连接扇区缓冲器的输出端点。 每个扇区缓冲器将时钟信号驱动到相应的一组负载。

公开(公告)号：US20130326456A1

公开(公告)日：2013-12-05

申请号：US13488065

申请日：2012-06-04

申请人： Charles Jay Alpert ,  Joseph Nicolas Kozhaya ,  Zhuo Li ,  Joseph J Palumbo ,  Haifeng Qian ,  Phillip John Restle ,  Chin Ngai Sze ,  Ying Zhou

发明人： Charles Jay Alpert ,  Joseph Nicolas Kozhaya ,  Zhuo Li ,  Joseph J Palumbo ,  Haifeng Qian ,  Phillip John Restle ,  Chin Ngai Sze ,  Ying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/62

摘要： An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.

摘要翻译： 具有接收器定位器单元的电子自动化设计工具基于平衡负载集群中的负载的大小并且基于每个集群的最小延迟，从时钟网络设计的扇区内的多个负载中产生负载集群，以及 在时钟网络设计的扇区中的多个接收器位置中的相应的一个。 该工具确定负载集群的中心，并确定与簇的中心对应的接收位置，以连接扇区缓冲器的输出端点。 每个扇区缓冲器将时钟信号驱动到相应的一组负载。

公开(公告)号：US07127696B2

公开(公告)日：2006-10-24

申请号：US10738711

申请日：2003-12-17

申请人： Charles Jay Alpert ,  Rama Gopal Gandham ,  Milos Hrkic ,  Stephen Thomas Quay

发明人： Charles Jay Alpert ,  Rama Gopal Gandham ,  Milos Hrkic ,  Stephen Thomas Quay

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/505

摘要： A mechanism for constructing Steiner trees using simultaneous blockage avoidance, delay optimization, and design density management are provided. An initial tiled timing-driven Steiner tree is obtained for an integrated circuit design. The Steiner tree is broken into 2-paths for which plates are generated designated the permissible area in which a Steiner point may migrate. Each 2-path is optimized by calculating a cost for each tile in the plate as a function of an environmental cost, a tile delay cost, and a trade-off value. A minimum cost tile is then selected as the point to which the Steiner point in the 2-path, if any, is to migrate. Once each 2-path is processed in this manner, routing is performed so as to minimize the cost at the source. This process may be iteratively repeated with new trade-off values until all of the nets have zero or positive slew.

摘要翻译： 提供了一种使用同时阻止避免，延迟优化和设计密度管理构建Steiner树的机制。 获得用于集成电路设计的初始平铺时序驱动的Steiner树。 Steiner树被分解为2路径，其中生成了板，指定Steiner点可能迁移的允许区域。 通过根据环境成本，瓦片延迟成本和折衷值计算板中每个瓦片的成本来优化每个2路径。 然后选择最小成本图块作为2路径中Steiner点（如果有）要迁移的点。 一旦以这种方式处理了每个2路径，就执行路由以最小化源的成本。 可以用新的权衡值迭代地重复该过程，直到所有网络具有零或正的摆动。

公开(公告)号：US07065730B2

公开(公告)日：2006-06-20

申请号：US10418469

申请日：2003-04-17

申请人： Charles Jay Alpert ,  Rama Gopal Gandham ,  Jiang Hu ,  Stephen Thomas Quay

发明人： Charles Jay Alpert ,  Rama Gopal Gandham ,  Jiang Hu ,  Stephen Thomas Quay

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method, computer program product, and data processing system for porosity-aware buffered Steiner tree construction are disclosed. A preferred embodiment begins with a timing-driven Steiner tree generated without regard for porosity, then applies a plate-based adjustment guided by length-based buffer insertion. After performing localized blockage avoidance, the resulting tree is then passed to a buffer placement algorithm, such as van Ginneken's algorithm, to obtain a porosity-aware buffered Steiner tree.

摘要翻译： 公开了一种用于孔隙度感知缓冲Steiner树结构的方法，计算机程序产品和数据处理系统。 优选实施例从不考虑孔隙率产生的定时驱动的Steiner树开始，然后施加基于长度的缓冲器插入引导的基于板的调整。 在执行局部阻止避免之后，所得到的树然后被传递到缓冲器放置算法，例如van Ginneken的算法，以获得孔隙度感知缓冲的Steiner树。