公开(公告)号：US20040084671A1

公开(公告)日：2004-05-06

申请号：US10288193

申请日：2002-11-05

申请人： Chartered Semiconductor Manufacturing Ltd.

发明人： Zhigang Song ,  Shailesh Redkar ,  Chong Khiam Oh

IPC分类号： H01L021/00 ,  G01R031/26 ,  H01L023/58

CPC分类号： H01L22/34 ,  G01R31/311 ,  Y10S257/911 ,  Y10S257/919

摘要： A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

摘要翻译： 实现了在集成电路器件的导电层中定位桥接缺陷的新的测试结构。 测试结构包括包括覆盖在衬底上的导电层的线。 线连接到地面。 多个矩形包括导电层。 矩形不连接到线或其他矩形。 矩形和线的近边是平行的。 矩形是浮动的。 测试结构与扫描电子显微镜中的被动电压对比度测试一起使用。 公开了一种测量关键尺寸的测试结构和方法。