公开(公告)号：US20120185231A1

公开(公告)日：2012-07-19

申请号：US13008921

申请日：2011-01-19

申请人： Chen-Kang LO ,  Li-Chun Chen ,  Meng-Huan Wu ,  Ren-Song Tsay

发明人： Chen-Kang LO ,  Li-Chun Chen ,  Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/68

摘要： The present invention discloses a cycle-count-accurate (CCA) processor modeling, which can achieve high simulation speeds while maintaining timing accuracy of the system simulation. The CCA processor modeling includes a pipeline subsystem model and a cache subsystem model with accurate cycle with accurate cycle count information and guarantees accurate timing and functional behaviors on processor interface. The CCA processor modeling further includes a branch predictor and a bus interface (BIF) to predict the branch of pipeline execution behavior (PEB) and to simulate the data accesses between the processor and the external components via an external bus, respectively. The experimental results show that the CCA processor modeling performs 50 times faster than the corresponding Cycle-accurate (CA) model while providing the same cycle count information as the target RTL model.

摘要翻译： 本发明公开了一种循环计数精确（CCA）处理器建模，可以实现高仿真速度，同时保持系统仿真的定时精度。 CCA处理器建模包括管道子系统模型和具有精确周期的缓存子系统模型，具有精确的周期计数信息，并保证处理器接口上的精确时序和功能行为。 CCA处理器建模还包括分支预测器和总线接口（BIF），以预测流水线执行行为（PEB）的分支，并分别通过外部总线模拟处理器与外部组件之间的数据访问。 实验结果表明，CCA处理器建模比相应的周期精确（CA）模型快50倍，同时提供与目标RTL模型相同的周期计数信息。