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公开(公告)号：US20210335189A1
公开(公告)日：2021-10-28
申请号：US16320390
申请日：2018-05-22
发明人： Yong YU , Yuan YAO , Chuanyan LAN , Taehyun KIM
IPC分类号： G09G3/20 , G06T5/00 , G09G3/3208 , G06F1/16
摘要： An image processing method, a drive device, a display panel, and a wearable device are disclosed. The image processing method includes: determining an adjacent display pixel adjacent to each grayscale transition region in the row direction or in the column direction in the display image region according to a position of the grayscale transition region; determining a transition pixel in the grayscale transition region; acquiring a first pixel grayscale, in which the first pixel grayscale is a grayscale of the adjacent display pixel; acquiring a second pixel grayscale; adjusting a third pixel grayscale of the transition pixel according to the first pixel grayscale, the second pixel grayscale and the transition pixel, in which the third pixel grayscale is between the first pixel grayscale and the second pixel grayscale; and transmitting the third pixel grayscale to the display panel for display.
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公开(公告)号：US20210335944A1
公开(公告)日：2021-10-28
申请号：US16492936
申请日：2019-02-02
发明人： Yonglin GUO , Tingliang LIU , Kai ZHANG , Yuan YAO , Yi ZHANG
摘要： Disclosed herein is a display substrate of a display panel, comprising: a support; a second layer on the support; a window extending through the second layer and optically coupled with an image sensor; and a sidewall at least partially surrounding the window; wherein the sidewall is configured to attenuate transmission of light through the sidewall.
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公开(公告)号：US20210166614A1
公开(公告)日：2021-06-03
申请号：US16062479
申请日：2017-11-08
发明人： Yuan YAO , Young Yik KO , Yue LONG , Wanli DONG
IPC分类号： G09G3/20 , G09G3/3291 , G09G3/3258
摘要： There is provided a pixel driving circuit and a driving method thereof, and a display apparatus. The pixel driving circuit includes a driving transistor, a storage capacitor, and a light emitting element, a first control sub-circuit and a second control sub-circuit; first and second control terminals of the first control sub-circuit are connected to first and second pulse signal terminals, a first input terminal thereof is connected to a power supply signal terminal and a source of a driving transistor, a second input terminal thereof is connected to an initial signal terminal, third and fourth input terminals thereof are connected to a data line and a drain of the driving transistor, a first output terminal thereof is connected to a first electrode plate of a storage capacitor, and a second output terminal thereof is connected to a second plate and a gate of the driving transistor.
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