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公开(公告)号：US07636653B1
公开(公告)日：2009-12-22
申请号：US11343367
申请日：2006-01-31
CPC分类号： G06F17/5027
摘要： An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.
摘要翻译： 与可编程设备上的基于软件的仿真工具和被测设计一起使用的以太网协同仿真界面可以包括主机接口和网络处理器。 主机接口可以在主机计算系统上执行，并促进基于软件的仿真工具与被测设计的通信链路之间的数据传输。 网络处理器可以在可编程设备内部实现，并促进通信链路和被测设计之间的数据传输。 主机接口和网络处理器可以通过点对点以太网连接交换格式化为原始以太网帧的模拟数据。
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公开(公告)号：US07707019B1
公开(公告)日：2010-04-27
申请号：US11234529
申请日：2005-09-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： A method of co-simulation involving a high level modeling system and an integrated circuit such as, e.g., a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.
摘要翻译： 涉及高级建模系统和诸如可编程逻辑器件（PLD）的集成电路的协同仿真的方法可以包括在写入PLD的至少一个输入端口时存储来自 协同仿真引擎，并且响应于发送条件，将多个命令作为单个事务发送到PLD。 当从PLD的至少一个输出端口读取时，根据高速缓存一致性的状态选择性地从PLD外部的高速缓存或PLD的存储器读取。
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公开(公告)号：US07346482B1
公开(公告)日：2008-03-18
申请号：US11075340
申请日：2005-03-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Co-simulation of a circuit design includes simulating a first subset of blocks of the circuit design on a software-based co-simulation platform, simulating a second subset of the blocks of the circuit design on a hardware-based co-simulation platform, and maintaining coherency for a memory block of the circuit design between a first representation of data in the memory block on the software-based co-simulation platform and a second representation of the data in the memory block on the hardware-based co-simulation platform. Coherency is maintained by managing mutually exclusive access to the memory block from the first subset of blocks and the second subset of blocks.
摘要翻译： 电路设计的协同仿真包括在基于软件的协同仿真平台上模拟电路设计的块的第一子集，在基于硬件的协同仿真平台上模拟电路设计的块的第二子集，以及 在基于软件的协同仿真平台的存储器块中的数据的第一表示和基于硬件的协同仿真平台的存储器块中的数据的第二表示之间维持电路设计的存储器块的一致性。 通过管理来自块的第一子集和块的第二子集的对存储器块的互斥访问来维持一致性。
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公开(公告)号：US07343572B1
公开(公告)日：2008-03-11
申请号：US11096024
申请日：2005-03-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A first block, a second block, a shared memory, and a third block are generated in a circuit design in response to user input control. The first block is coupled to the second block, the second block is coupled to the shared memory, and the shared memory is coupled to the third block in response to user input control. During one cycle of a simulation, the second block, in response to the first block, accesses a set of scalar values in the shared memory using scalar accesses. During one cycle of the simulation, the set of scalar values is transferred between the second block and the first block. During the simulation, the shared memory is accessed by the third block using scalar accesses.
摘要翻译： 响应于用户输入控制，在电路设计中产生第一块，第二块，共享存储器和第三块。 第一块耦合到第二块，第二块耦合到共享存储器，并且响应于用户输入控制，共享存储器耦合到第三块。 在仿真的一个周期期间，响应于第一个块，第二个块使用标量访问访问共享存储器中的一组标量值。 在模拟的一个周期期间，标量值集合在第二块和第一块之间传送。 在仿真期间，使用标量访问由第三块访问共享存储器。
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5.发明授权Specification of the hierarchy, connectivity, and graphical representation of a circuit design 有权电路设计的层次结构，连接性和图形表示的规范公开(公告)号：US07003751B1
公开(公告)日：2006-02-21
申请号：US10340498
申请日：2003-01-10
申请人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
发明人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity attributes, and display attributes that describe a plurality of modules. The hierarchy attributes define parent-child relationships between modules, the connectivity attributes define input-output connections between modules, and the display attributes define a layout of the modules for viewing. Each of the objects has an associated method for generating a design specification in a selected format. When the program is executed, the design specification is generated from the set of objects. Depending on the capabilities of the available tools, the modules and logic elements are displayed in accordance with the display attributes either from the object-oriented program or from the design specification.
摘要翻译： 用于创建电路设计的方法和装置。 面向对象的程序实例化建模电路设计的多个对象。 对象具有描述多个模块的层次属性，连接属性和显示属性。 层次结构属性定义模块之间的父子关系，连接属性定义模块之间的输入输出连接，显示属性定义模块的布局以供查看。 每个对象具有用于以所选格式生成设计规范的关联方法。 当执行程序时，设计规范是从对象集合生成的。 根据可用工具的功能，根据面向对象程序或设计规范的显示属性显示模块和逻辑元素。
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公开(公告)号：US07739092B1
公开(公告)日：2010-06-15
申请号：US11343554
申请日：2006-01-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5022
摘要： A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.
摘要翻译： 复位用于硬件协同仿真的可编程逻辑器件（PLD）的方法可以包括将完整比特流加载到PLD中。 完整的比特流可以用PLD来编程以用于第一次仿真的电路设计。 该方法还可以包括将部分比特流加载到PLD中，从而重置不具有复位功能的电路设计的至少一个组件，使得电路设计被初始化以用于随后的模拟。
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公开(公告)号：US07478030B1
公开(公告)日：2009-01-13
申请号：US10600848
申请日：2003-06-19
CPC分类号： G06F17/5027 , G06F2217/62
摘要： Method and apparatus for clock stabilization detection for hardware simulation is described. More particularly, a lock signal is obtained, for example from a digital clock module. A least common multiple (LCM) clock signal is generated, for example from a clock module. A control signal is generated at least partially responsive to the LCM clock signal and the lock signal. The control signal may be generated from a state machine and applied to select circuitry, where the control signal is used to mask application of the output clock signal responsive to the control signal.
摘要翻译： 描述了用于硬件模拟的时钟稳定检测的方法和装置。 更具体地，例如从数字时钟模块获得锁定信号。 例如从时钟模块产生最小公共多（LCM）时钟信号。 至少部分地响应于LCM时钟信号和锁定信号产生控制信号。 控制信号可以从状态机产生并应用于选择电路，其中控制信号用于响应于控制信号屏蔽输出时钟信号的应用。
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8.发明授权公开(公告)号：US07437280B1
公开(公告)日：2008-10-14
申请号：US11016378
申请日：2004-12-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Co-simulation of an electronic circuit design using an embedded processor on a programmable logic device (PLD). The programmable logic resources of a PLD are used to perform hardware-based co-simulation of a first portion of the electronic circuit design. Software-based co-simulation of a second portion of the electronic circuit design is performed using the embedded processor.
摘要翻译： 使用可编程逻辑器件（PLD）上的嵌入式处理器进行电子电路设计的协同仿真。 PLD的可编程逻辑资源用于执行电子电路设计的第一部分的基于硬件的协同仿真。 使用嵌入式处理器执行电子电路设计的第二部分的基于软件的协同仿真。
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公开(公告)号：US07363600B1
公开(公告)日：2008-04-22
申请号：US10691343
申请日：2003-10-21
CPC分类号： G06F17/5022
摘要： A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.
摘要翻译： 在支持单向数据流的高级建模系统中对设计建模的方法可以包括识别总线块以表示系统中双向总线的连接性。 总线块可以与总线串联表示。 分接头可以通过总线接口连接总线。 在仿真期间，总线模块仿真与分接口的输入线串联的三态缓冲器的行为。 在合成期间，可以模拟总线端口到总线块的相反数据路由取向的单向输入和输出线对可以被折叠到单个总线端口。 该合成可以进一步生成可以在抽头输入和总线之间设置三态缓冲器的网表。 网表还可以表示用于驱动水龙头输出的三态缓冲器的布局。
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公开(公告)号：US07284225B1
公开(公告)日：2007-10-16
申请号：US10850133
申请日：2004-05-20
CPC分类号： G06F17/5054 , G06F2217/86
摘要： Various approaches for interfacing an application-independent hardware object with an application system are disclosed. The various approaches involve instantiating a first object that contains at least one configuration parameter. The configuration parameter specifies a location of a configuration bitstream for implementing functions of the hardware object in a programmable logic circuit. A second object is instantiated and is configured to open, in response to a program call to a first function provided by the second object, an interface to the programmable logic circuit. A programmable logic circuit is configured with the configuration bitstream in response to instantiation of the second object, and, in response to a program call to the first function, an interface to the programmable logic circuit is opened.
摘要翻译： 公开了用于将应用无关硬件对象与应用系统连接的各种方法。 各种方法涉及实例化包含至少一个配置参数的第一对象。 配置参数指定用于在可编程逻辑电路中实现硬件对象的功能的配置比特流的位置。 第二个对象被实例化并且被配置为响应于对由第二对象提供的第一功能的程序调用而打开到可编程逻辑电路的接口。 可编程逻辑电路被配置为响应于第二对象的实例化而具有配置比特流，并且响应于对第一功能的程序调用，打开到可编程逻辑电路的接口。
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