公开(公告)号：US07545178B2

公开(公告)日：2009-06-09

申请号：US11853712

申请日：2007-09-11

申请人： Chi-Chang Hung ,  Yung-Sheng Wei ,  Meng-Hsiu Wei

发明人： Chi-Chang Hung ,  Yung-Sheng Wei ,  Meng-Hsiu Wei

IPC分类号： H03K19/082

CPC分类号： H03K19/017509 ,  H03K5/2481 ,  H04L25/0272 ,  H04L25/085 ,  H04L25/49

摘要： A signal encoder and a signal decoder involves the signal encoder for receiving a data signal and a clock signal, including a first code output terminal and a second code output terminal. When the data signal is logic one, the signal encoder outputs a modulated signal through the first code output terminal, and outputs a fixed level signal through the second code output terminal. When the data signal is logic zero, the signal encoder outputs the fixed level signal through the first code output terminal, and outputs the modulated signal through the second code output terminal. The signal decoder converts the modulated signal and the fixed level signal output from the signal encoder into the data signal and the clock signal.

摘要翻译： 信号编码器和信号解码器涉及用于接收数据信号的信号编码器和包括第一代码输出端子和第二代码输出端子的时钟信号。 当数据信号为逻辑1时，信号编码器通过第一代码输出端输出调制信号，并通过第二代码输出端输出固定电平信号。 当数据信号为逻辑0时，信号编码器通过第一代码输出端输出固定电平信号，并通过第二代码输出端输出调制信号。 信号解码器将从信号编码器输出的调制信号和固定电平信号转换为数据信号和时钟信号。

公开(公告)号：US08135011B2

公开(公告)日：2012-03-13

申请号：US12134258

申请日：2008-06-06

申请人： Meng-Hsiu Wei ,  Hsien-Jen Chang ,  Chi-Chang Hung ,  Yung-Sheng Wei

发明人： Meng-Hsiu Wei ,  Hsien-Jen Chang ,  Chi-Chang Hung ,  Yung-Sheng Wei

IPC分类号： H04L12/56

CPC分类号： H05B37/0254 ,  H05B33/0842

摘要： The present invention provides method for operating a multipoint control system, which includes a plurality of controlled units serially connected and each controlled unit has a execution unit and an interpretive unit having a data processing unit and a memory unit, utilizes start packets pass through every one of controlled units which could be modified and transmitted to the next stage to achieve addressing for all of the system. Specifically, an information stream including a first start packet including a first leading message and a plurality of first data packets are transmitted by a controller, and a first address in the first start packet is modified by data processing unit and transmitted to the next stage. In addition, a first data packet corresponding to the first address is retrieved by the interpretive unit and the execution unit is enabled by the interpretive unit.

摘要翻译： 本发明提供了一种操作多点控制系统的方法，该多点控制系统包括串联连接的多个受控单元，每个受控单元具有执行单元和具有数据处理单元和存储单元的解释单元，利用每一个通过的起始分组 的受控单元，可以修改并传输到下一个阶段，以实现所有系统的寻址。 具体而言，由控制器发送包括包含第一前导消息和多个第一数据包的第一起始包的信息流，并且由数据处理单元修改第一起始包中的第一地址并发送到下一个阶段。 此外，解释单元检索对应于第一地址的第一数据分组，并且解释单元启用执行单元。

公开(公告)号：US07071992B2

公开(公告)日：2006-07-04

申请号：US10090176

申请日：2002-03-04

申请人： Chang-Lun Chen ,  Hsiao-Ming Huang ,  Meng-Hsiu Wei

发明人： Chang-Lun Chen ,  Hsiao-Ming Huang ,  Meng-Hsiu Wei

IPC分类号： H04N7/01

CPC分类号： G09G5/008 ,  G09G5/391 ,  H04N7/01 ,  H04N7/0105

摘要： A video format bridge employs a plurality of techniques to insure that the line buffer does not suffer underflow or overflow conditions, and that the output frame rate matches the input frame rate. The bridge handles the problem of residue lines, addresses fluctuations in the input and output clock rates, and allows adjustment of the ratio of the input and output the number of lines per frame or number of pixels per line so that output device specifications are not exceeded. A single integrated circuit may provided which is adapted to perform a plurality of techniques, and includes resources by which the user is able to enable and disable such techniques as needed for the particular bridging operation being executed. Bridge logic produces an output video stream which has an output frame rate matching the input frame rate, and in which the output frame has at least one of a variable number of pixels per line within an output frame, and/or a variable number of lines per frame among output frames in a set of more than one output frames.