公开(公告)号：US06255172B1

公开(公告)日：2001-07-03

申请号：US09567918

申请日：2000-05-10

申请人： Chih-Jen Huang ,  Auter Wu ,  Shih-Fang Hong

发明人： Chih-Jen Huang ,  Auter Wu ,  Shih-Fang Hong

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L21/28273

摘要： A method of manufacturing an electrically erasable non-volatile memory is suitable for use on a substrate. The method includes the following steps. First, a tunnel oxide layer is formed on the substrate. A floating gate and a silicon oxide layer/silicon nitride/silicon oxide layer is formed in order on the tunnel oxide layer. Next, a first oxide layer and a silicon nitride spacer are formed in order on the sidewalls of the floating gate. A second oxide layer is formed along the surface of the above entire structure. A third oxide layer is formed on the substrate on both sides of the silicon nitride spacer by oxidation. A patterned conductive layer on the substrate to serve as a control gate and a select transistor gate is formed above the substrate. Using the select transistor gate as a mask, the exposed part of the third oxide layer is removed to make the residual third oxide layer serve as a gate oxide layer of the select transistor. Finally, ion implantation is performed on the substrate to form source and drain regions.

摘要翻译： 制造电可擦除非易失性存储器的方法适用于基板。 该方法包括以下步骤。 首先，在基板上形成隧道氧化层。 在隧道氧化物层上依次形成浮置栅极和氧化硅层/氮化硅/氧化硅层。 接下来，在浮栅的侧壁上依次形成第一氧化物层和氮化硅间隔物。 沿着上述整个结构的表面形成第二氧化物层。 通过氧化在氮化硅间隔物的两侧的基板上形成第三氧化物层。 在衬底上形成用作控制栅极和选择晶体管栅极的图案化导电层。 使用选择晶体管栅极作为掩模，去除第三氧化物层的暴露部分，使剩余的第三氧化物层用作选择晶体管的栅极氧化物层。 最后，在衬底上进行离子注入以形成源区和漏区。

公开(公告)号：US07807532B2

公开(公告)日：2010-10-05

申请号：US11623048

申请日：2007-01-12

申请人： Li Jiang ,  Ying Shao ,  Libbert Peng ,  Auter Wu

发明人： Li Jiang ,  Ying Shao ,  Libbert Peng ,  Auter Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/76224 ,  H01L27/11521 ,  H01L29/66545 ,  H01L29/66825

摘要： A method for processing semiconductor devices includes providing a semiconductor substrate. The method includes forming a pad oxide layer overlying the substrate and forming a silicon nitride layer overlying the pad oxide layer. The method includes forming a trench region extending through an entirety of a portion of the silicon nitride layer and extends into a depth of the semiconductor substrate. The method also includes filling the trench region with an oxide material. The oxide material extends from a bottom portion of the trench region to an upper surface of the silicon nitride layer. The method includes planarizing the oxide material and selectively removing the silicon nitride layer to form an isolation structure. A polysilicon material is deposited overlying the isolation structure. The polysilicon material is planarized to expose a top portion of the isolation structure and form a first electrode and a second electrode structures separated by a portion of the isolation structure.

摘要翻译： 半导体器件的处理方法包括提供半导体衬底。 该方法包括形成覆盖衬底的衬垫氧化层，并形成覆盖衬垫氧化物层的氮化硅层。 该方法包括形成延伸穿过氮化硅层的整个部分并延伸到半导体衬底的深度的沟槽区域。 该方法还包括用氧化物材料填充沟槽区域。 氧化物材料从沟槽区域的底部延伸到氮化硅层的上表面。 该方法包括平坦化氧化物材料并选择性地去除氮化硅层以形成隔离结构。 沉积在隔离结构上的多晶硅材料。 将多晶硅材料平坦化以暴露隔离结构的顶部，并形成由隔离结构的一部分隔开的第一电极和第二电极结构。

公开(公告)号：US20070243685A1

公开(公告)日：2007-10-18

申请号：US11623048

申请日：2007-01-12

申请人： Li Jiang ,  Ying Shao ,  Libbert Peng ,  Auter Wu

发明人： Li Jiang ,  Ying Shao ,  Libbert Peng ,  Auter Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/76224 ,  H01L27/11521 ,  H01L29/66545 ,  H01L29/66825

摘要： A method for processing semiconductor devices includes providing a semiconductor substrate. The method includes forming a pad oxide layer overlying the substrate and forming a silicon nitride layer overlying the pad oxide layer. The method includes forming a trench region extending through an entirety of a portion of the silicon nitride layer and extends into a depth of the semiconductor substrate. The method also includes filling the trench region with an oxide material. The oxide material extends from a bottom portion of the trench region to an upper surface of the silicon nitride layer. The method includes planarizing the oxide material and selectively removing the silicon nitride layer to form an isolation structure. A polysilicon material is deposited overlying the isolation structure. The polysilicon material is planarized to expose a top portion of the isolation structure and form a first electrode and a second electrode structures separated by a portion of the isolation structure.

摘要翻译： 半导体器件的处理方法包括提供半导体衬底。 该方法包括形成覆盖衬底的衬垫氧化层，并形成覆盖衬垫氧化物层的氮化硅层。 该方法包括形成延伸穿过氮化硅层的整个部分并延伸到半导体衬底的深度的沟槽区域。 该方法还包括用氧化物材料填充沟槽区域。 氧化物材料从沟槽区域的底部延伸到氮化硅层的上表面。 该方法包括平坦化氧化物材料并选择性地去除氮化硅层以形成隔离结构。 沉积在隔离结构上的多晶硅材料。 将多晶硅材料平坦化以暴露隔离结构的顶部，并形成由隔离结构的一部分隔开的第一电极和第二电极结构。