公开(公告)号：US08363777B2

公开(公告)日：2013-01-29

申请号：US13604632

申请日：2012-09-06

Applicant: Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

Inventor： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract translation: 移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。 每个移位寄存器级包括上拉单元，上拉控制单元，输入单元，第一下拉单元，第二下拉单元和下拉控制单元。 上拉控制单元根据驱动控制电压和第一时钟产生第一控制信号。 上拉单元根据第一控制信号上拉相应的门信号。 输入单元用于根据具有与第一时钟相反的相位的第二时钟输入前一移位寄存器级的门信号以变为驱动控制电压。 下拉控制单元根据驱动控制电压产生第二控制信号。 第一和第二下拉单元根据第二控制信号分别下拉对应的门信号和第一控制信号。

公开(公告)号：US08284891B2

公开(公告)日：2012-10-09

申请号：US13468047

申请日：2012-05-10

Applicant: Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

Inventor： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

公开(公告)号：US20120219105A1

公开(公告)日：2012-08-30

申请号：US13468047

申请日：2012-05-10

Applicant: Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

Inventor： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

IPC: G11C19/36 ,  G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract translation: 移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。 每个移位寄存器级包括上拉单元，上拉控制单元，输入单元，第一下拉单元，第二下拉单元和下拉控制单元。 上拉控制单元根据驱动控制电压和第一时钟产生第一控制信号。 上拉单元根据第一控制信号上拉相应的门信号。 输入单元用于根据具有与第一时钟相反的相位的第二时钟输入前一移位寄存器级的门信号以变为驱动控制电压。 下拉控制单元根据驱动控制电压产生第二控制信号。 第一和第二下拉单元根据第二控制信号分别下拉对应的门信号和第一控制信号。

公开(公告)号：US20110142192A1

公开(公告)日：2011-06-16

申请号：US12959378

申请日：2010-12-03

Applicant: Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

Inventor： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract translation: 移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。 每个移位寄存器级包括上拉单元，上拉控制单元，输入单元，第一下拉单元，第二下拉单元和下拉控制单元。 上拉控制单元根据驱动控制电压和第一时钟产生第一控制信号。 上拉单元根据第一控制信号上拉相应的门信号。 输入单元用于根据具有与第一时钟相反的相位的第二时钟输入前一移位寄存器级的门信号以变为驱动控制电压。 下拉控制单元根据驱动控制电压产生第二控制信号。 第一和第二下拉单元根据第二控制信号分别下拉对应的门信号和第一控制信号。

公开(公告)号：US20120120035A1

公开(公告)日：2012-05-17

申请号：US13204941

申请日：2011-08-08

Applicant: Yu-Chung YANG ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Kuo-Hua Hsu ,  Chih-Ying Lin ,  Kun-Yueh Lin

Inventor： Yu-Chung YANG ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Kuo-Hua Hsu ,  Chih-Ying Lin ,  Kun-Yueh Lin

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2310/0205

Abstract: A LCD panel with an improved pixel array configuration is provided. The LCD panel uses a column inversion driving method to drive the data lines so as to achieve a stable common voltage. Moreover, by cross-connecting the layout traces of the wiring zone in a specified manner, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.

Abstract translation: 提供了具有改进的像素阵列配置的LCD面板。 LCD面板使用列反转驱动方法驱动数据线，以达到稳定的公共电压。 此外，通过以指定的方式交叉连接布线区的布局迹线，从与子像素相邻的每两个栅极线输出的栅极脉冲彼此不重叠，从而可以正常显示该帧。

公开(公告)号：US08723772B2

公开(公告)日：2014-05-13

申请号：US13204941

申请日：2011-08-08

Applicant: Yu-Chung Yang ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Kuo-Hua Hsu ,  Chih-Ying Lin ,  Kun-Yueh Lin

Inventor： Yu-Chung Yang ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Kuo-Hua Hsu ,  Chih-Ying Lin ,  Kun-Yueh Lin

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2310/0205

Abstract: A LCD panel with an improved pixel array configuration is provided. The LCD panel uses a column inversion driving method to drive the data lines so as to achieve a stable common voltage. Moreover, by cross-connecting the layout traces of the wiring zone in a specified manner, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.

Abstract translation: 提供了具有改进的像素阵列配置的LCD面板。 LCD面板使用列反转驱动方法驱动数据线，以达到稳定的公共电压。 此外，通过以指定的方式交叉连接布线区的布局迹线，从与子像素相邻的每两个栅极线输出的栅极脉冲彼此不重叠，从而可以正常显示该帧。

公开(公告)号：US20120328070A1

公开(公告)日：2012-12-27

申请号：US13604632

申请日：2012-09-06

Applicant: Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

Inventor： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

IPC: G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

公开(公告)号：US08204170B2

公开(公告)日：2012-06-19

申请号：US12959378

申请日：2010-12-03

Applicant: Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

Inventor： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract translation: 移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。 每个移位寄存器级包括上拉单元，上拉控制单元，输入单元，第一下拉单元，第二下拉单元和下拉控制单元。 上拉控制单元根据驱动控制电压和第一时钟产生第一控制信号。 上拉单元根据第一控制信号上拉相应的门信号。 输入单元用于根据具有与第一时钟相反的相位的第二时钟输入前一移位寄存器级的门信号以变为驱动控制电压。 下拉控制单元根据驱动控制电压产生第二控制信号。 第一和第二下拉单元根据第二控制信号分别下拉对应的门信号和第一控制信号。

公开(公告)号：US20120235890A1

公开(公告)日：2012-09-20

申请号：US13481955

申请日：2012-05-28

Applicant: Kuo-Hua Hsu ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Chang Su

Inventor： Kuo-Hua Hsu ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Chang Su

IPC: G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3674 ,  G09G2310/0286

Abstract: A shift register of an LCD device includes a plurality of shift register units coupled in series. Each shift register unit includes an input circuit and a pull-down circuit having symmetric structures which enable the LCD device to function in a forward-scan mode and a reverse-scan mode.

Abstract translation: LCD装置的移位寄存器包括串联耦合的多个移位寄存器单元。 每个移位寄存器单元包括具有对称结构的输入电路和下拉电路，使得LCD器件能够以正向扫描模式和反向扫描模式工作。

公开(公告)号：US08218713B2

公开(公告)日：2012-07-10

申请号：US12899541

申请日：2010-10-06

Applicant: Kuo-Hua Hsu ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Chang Su

Inventor： Kuo-Hua Hsu ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Chang Su

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3674 ,  G09G2310/0286

Abstract: A shift register of an LCD device includes a plurality of shift register units coupled in series. Each shift register unit includes an input circuit and a pull-down circuit having symmetric structures which enable the LCD device to function in a forward-scan mode and a reverse-scan mode.

Abstract translation: LCD装置的移位寄存器包括串联耦合的多个移位寄存器单元。 每个移位寄存器单元包括具有对称结构的输入电路和下拉电路，使得LCD器件能够以正向扫描模式和反向扫描模式工作。