GATE DRIVE CIRCUIT, ARRAY SUBSTRATE, AND DISPLAY DEVICE

    公开(公告)号:US20210256930A1

    公开(公告)日:2021-08-19

    申请号:US16647671

    申请日:2019-04-01

    IPC分类号: G09G3/36 G11C19/28

    摘要: The present disclosure provides a gate drive circuit, an array substrate, and a display device. The gate drive circuit includes cascaded shift registers, control circuits, level shifters, voltage stabilization circuits, and first exchanging circuits. The shift registers at respective stages output respective first signals. Each control circuit is configured to process the respective first signal to generate a respective second signal. Each level shifter is configured to convert the voltage level of the respective second signal to generate a respective third signal. Each voltage stabilization circuit is configured to stabilize the respective third signal. The stabilized third signal is outputted as a fourth signal. The first exchanging circuit is configured to enable any of the following: exchanging the first signals at two adjacent stages, exchanging the second signals at two adjacent stages, exchanging the third signals at two adjacent stages, and exchanging the fourth signals at two adjacent stages.

    GOA CIRCUIT AND DRIVING METHOD THEREOF, AND TOUCH DISPLAY APPARATUS

    公开(公告)号:US20190311690A1

    公开(公告)日:2019-10-10

    申请号:US16374558

    申请日:2019-04-03

    IPC分类号: G09G3/36 G06F3/041

    摘要: A GOA circuit includes a plurality of GOA units. First input terminals of a first-level GOA unit to a (N/2)th-level GOA unit are coupled to a first signal terminal, and a first input terminal of any one of other GOA units is coupled to an output terminal of a (N/2)th-level GOA unit located in front of the any one of other GOA units. Second input terminals of a last-level GOA unit to a (N/2)th last-level GOA unit are coupled to a second signal terminal, and a second input terminal of any one of other GOA units is coupled to an output terminal of a (N/2)th-level GOA unit located behind the any one of other GOA units. N is the number of clock signals in one clock period. N/2 cascaded GOA units of the GOA circuit are included in a pull-up node potential holding unit, and output terminals of the N/2 cascaded GOA units are not coupled to gate lines.