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公开(公告)号：US20190043897A1
公开(公告)日：2019-02-07
申请号：US16023840
申请日：2018-06-29
发明人： Maokun TIAN , Wei SHEN , Zhonghao HUANG , Zhaojun WANG , Dalong MAO
IPC分类号： H01L27/12
摘要： The present disclosure describes a method for fabricating an array substrate, an array substrate, and a display device. The method includes the following steps: forming a gate electrode on a substrate; forming a gate insulating layer on a side of the gate electrode distal to the substrate; and forming an active layer and a source-drain metal sequentially on a side of the gate insulating layer distal to the gate electrode; forming a protection layer for the source-drain metal on a side of the source-drain metal distal to the gate insulating layer; and etching portion of the source-drain metal corresponding to the channel region to form a source electrode and a drain electrode.
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2.发明申请公开(公告)号：US20200035835A1
公开(公告)日：2020-01-30
申请号：US16502619
申请日：2019-07-03
发明人： Hongru ZHOU , Kai WANG , Kunkun GAO , Xiaonan DONG , Zhaojun WANG
IPC分类号： H01L29/786 , H01L29/417 , H01L29/423 , H01L29/66
摘要： There is provided a thin film transistor including: a substrate; a gate electrode and a first electrode in a single layer on the substrate; an active layer above the first electrode, an orthographic projection of the active layer on the substrate at least partially covers an orthographic projection of the first electrode on the substrate; a first insulation layer covering the gate electrode, the first electrode, the active layer, a portion of the substrate exposed between the gate electrode and the active layer, and another portion of the substrate exposed between the gate electrode and the first electrode; and a second electrode above the first insulation layer, an orthographic projection of the second electrode on the substrate at least partially covers the orthographic projection of the active layer on the substrate, and the second electrode is connected to the active layer through a via-hole in the first insulation layer.
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3.发明申请公开(公告)号：US20220344377A1
公开(公告)日：2022-10-27
申请号：US17432105
申请日：2021-02-01
发明人： Zhiyong NING , Zhonghao HUANG , Chao ZHANG , Zhaojun WANG , Hongru ZHOU , Yutong YANG , Rui WANG , Xu WU , Kunkun GAO
IPC分类号： H01L27/12
摘要： A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.
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