公开(公告)号：US20060143260A1

公开(公告)日：2006-06-29

申请号：US11209664

申请日：2005-08-24

Applicant: Chuan-Cheng Peng ,  Wei-Bin Yang

Inventor： Chuan-Cheng Peng ,  Wei-Bin Yang

IPC: G06F7/52

CPC classification number: G06F7/5338

Abstract: A low-power Booth array multiplier with bypass circuits is provided. The multiplier includes a first encoder for Booth-encoding the multiplier; a second encoder for pre-encoding the multiplier to generate an enabling signal and a plurality of control signals, wherein the control signals are used for determining whether to process partial product calculations or not; a selector for generating partial products according to the encoding results from the first encoder and the multiplicand; an adder array, which is composed of a plurality of adders for summing up the partial products. The adder includes a first multiplexer and a second multiplexer. When an adder of one row is disabled by the enabling signal, the first multiplexer receives a summation of the former row and the second multiplexer receives the carry bit of the former row. The multiplier further includes a plurality of third multiplexers for outputting the summation of the adder array.

Abstract translation: 提供具有旁路电路的低功率布斯阵列乘法器。 乘法器包括用于布尔编码乘法器的第一编码器; 用于对所述乘法器进行预编码以产生使能信号和多个控制信号的第二编码器，其中所述控制信号用于确定是否处理部分乘积运算; 用于根据来自第一编码器和被乘数的编码结果产生部分乘积的选择器; 加法器阵列，其由用于求和部分乘积的多个加法器组成。 加法器包括第一多路复用器和第二多路复用器。 当一行的加法器被使能信号禁用时，第一多路复用器接收前一行的求和并且第二多路复用器接收前一行的进位位。 乘法器还包括用于输出加法器阵列的求和的多个第三多路复用器。

公开(公告)号：US20080172546A1

公开(公告)日：2008-07-17

申请号：US11679028

申请日：2007-02-26

Applicant: Chuan-Cheng Peng ,  Po-Han Huang

Inventor： Chuan-Cheng Peng ,  Po-Han Huang

IPC: G06F15/76

CPC classification number: G06F9/3012 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/342 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3885 ,  G06F9/3891

Abstract: A digital signal processor is provided, comprising at least one cluster. The cluster may comprise at least two function units each conducting different instruction types, at least two private register files each associated with one function unit for data storage, a ping-pong register providing exclusively accessible data storage, and a public register file. The public register file comprises at least two read ports, each coupled to a function unit, providing read accessibility for the function units, and one write port to write data to the public register file.

Abstract translation: 提供了一种数字信号处理器，包括至少一个群集。 集群可以包括至少两个功能单元，每个功能单元执行不同的指令类型，每个与用于数据存储的一个功能单元相关联的至少两个专用寄存器文件，提供专用可访问数据存储器的乒乓寄存器和公共寄存器文件。 公共登记文件包括至少两个读端口，每个读端口耦合到功能单元，提供功能单元的读取可访问性，以及一个写入端口将数据写入公共寄存器文件。

公开(公告)号：US07581086B2

公开(公告)日：2009-08-25

申请号：US11679028

申请日：2007-02-26

Applicant: Chuan-Cheng Peng ,  Po-Han Huang

Inventor： Chuan-Cheng Peng ,  Po-Han Huang

IPC: G06F9/312

CPC classification number: G06F9/3012 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/342 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3885 ,  G06F9/3891

Abstract: A digital signal processor is provided, comprising at least one cluster. The cluster may comprise at least two function units each conducting different instruction types, at least two private register files each associated with one function unit for data storage, a ping-pong register providing exclusively accessible data storage, and a public register file. The public register file comprises at least two read ports, each coupled to a function unit, providing read accessibility for the function units, and one write port to write data to the public register file.

Abstract translation: 提供了一种数字信号处理器，包括至少一个群集。 集群可以包括至少两个功能单元，每个功能单元执行不同的指令类型，每个与用于数据存储的一个功能单元相关联的至少两个专用寄存器文件，提供专用可访问数据存储器的乒乓寄存器和公共寄存器文件。 公共登记文件包括至少两个读端口，每个读端口耦合到功能单元，提供功能单元的读取可访问性，以及一个写入端口将数据写入公共寄存器文件。

公开(公告)号：US20070239970A1

公开(公告)日：2007-10-11

申请号：US11278824

申请日：2006-04-06

Applicant: I-Tao Liao ,  Chuan-Cheng Peng ,  Po-Han Huang ,  Chuan-Hua Chang

Inventor： I-Tao Liao ,  Chuan-Cheng Peng ,  Po-Han Huang ,  Chuan-Hua Chang

IPC: G06F9/44

CPC classification number: G06F9/3012 ,  G06F9/30141 ,  G06F9/3836 ,  G06F9/3885 ,  G06F9/3891

Abstract: An apparatus for cooperative sharing of operand access port of a banked register file comprises a partitioned register file, a first group of functional unit, a second group of function units and an access control circuit. The access control circuit includes three control bits to control the accesses to the register file by the functional units for operands. The invention is to relax the constraint encountered by the compiler and a smart assembler using a conventional Ping-Pong file register. The relaxed constraint allows the two banks of the partitioned register file accessed by two instructions simultaneously as long as each corresponding operand of the two instructions are in different register banks. By the relaxed constraint, a compiler and a smart assembler have more choices to schedule instructions in a program, potentially increasing program performance.

Abstract translation: 一种用于协同共享存储寄存器文件的操作数访问端口的装置，包括分区寄存器文件，第一组功能单元，第二组功能单元和访问控制电路。 访问控制电路包括三个控制位，用于控制功能单元对操作数对寄存器文件的访问。 本发明是为了放松使用传统乒乓文件寄存器的编译器和智能汇编器遇到的约束。 宽松的约束允许两个指令同时访问的分区寄存器文件的两个库，只要两个指令的每个相应的操作数都在不同的寄存器组中。 通过轻松的约束，编译器和智能汇编器有更多的选择来调度程序中的指令，从而潜在地增加程序性能。