公开(公告)号：US06583785B2

公开(公告)日：2003-06-24

申请号：US09777247

申请日：2001-02-05

Applicant: Chun Lin Yeh

Inventor： Chun Lin Yeh

IPC: G09G500

CPC classification number: G09G5/18

Abstract: A variable clock rate device and a method of operating the device. When the display device is first initialized, a pixel clock and a memory read clock are set to the largest values. If the CPU reads from the memory area, the frequency of the pixel clock and the memory read clock is adjusted according to the frequency of the CPU update on-screen memory and the variation of the CPU change on-screen memory block. On the contrary, if the CPU does not initiate any updating, the pixel clock and the memory read clock are tuned down to the smallest possible values to conserve electricity.