公开(公告)号：US08772120B2

公开(公告)日：2014-07-08

申请号：US13479279

申请日：2012-05-24

申请人： Chung-Fu Chang ,  Yu-Hsiang Hung ,  Shin-Chuan Huang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou

发明人： Chung-Fu Chang ,  Yu-Hsiang Hung ,  Shin-Chuan Huang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864

摘要： A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers.

摘要翻译： 半导体工艺包括以下步骤。 在基板上形成栅极结构。 在栅极结构旁边的基板上形成主间隔物。 源极/漏极形成在主间隔物旁边的衬底中。 在形成源极/漏极之后，在主间隔物旁边的衬底中形成外延结构。 栅极结构可以分别形成在衬底的第一区域和第二区域中。 在衬底上分别在两个栅极结构旁边形成主间隔物。 源极/漏极分别在两个间隔物的旁边的衬底中形成。 在形成两个源极/漏极之后，在主衬垫的旁边分别在衬底中形成外延结构。

公开(公告)号：US20130316506A1

公开(公告)日：2013-11-28

申请号：US13479279

申请日：2012-05-24

申请人： Chung-Fu Chang ,  Yu-Hsiang Hung ,  Shin-Chuan Huang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou

发明人： Chung-Fu Chang ,  Yu-Hsiang Hung ,  Shin-Chuan Huang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864

摘要： A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers.

摘要翻译： 半导体工艺包括以下步骤。 在基板上形成栅极结构。 在栅极结构旁边的基板上形成主间隔物。 源极/漏极形成在主间隔物旁边的衬底中。 在形成源极/漏极之后，在主间隔物旁边的衬底中形成外延结构。 栅极结构可以分别形成在衬底的第一区域和第二区域中。 在衬底上分别在两个栅极结构旁边形成主间隔物。 源极/漏极分别在两个间隔物的旁边的衬底中形成。 在形成两个源极/漏极之后，在主衬垫的旁边分别在衬底中形成外延结构。

公开(公告)号：US20130089962A1

公开(公告)日：2013-04-11

申请号：US13270240

申请日：2011-10-11

申请人： Chung-Fu Chang ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Chia-Jong Liu ,  Pei-Yu Chou ,  Jyh-Shyang Jenq ,  Ling-Chun Chou ,  I-Chang Wang ,  Ching-Wen Hung ,  Ted Ming-Lang Guo ,  Chun-Yuan Wu

发明人： Chung-Fu Chang ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Chia-Jong Liu ,  Pei-Yu Chou ,  Jyh-Shyang Jenq ,  Ling-Chun Chou ,  I-Chang Wang ,  Ching-Wen Hung ,  Ted Ming-Lang Guo ,  Chun-Yuan Wu

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

摘要： A semiconductor process includes the following steps. A substrate is provided. A gate structure is formed on the substrate. A spacer is formed on the substrate beside the gate structure. The spacer includes a first spacer and a second spacer located on the external surface of the first spacer. A first etching process is performed to etch and form at least a recess in the substrate beside the spacer and entirely remove the second spacer. The etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer. An epitaxial layer is formed in the recess.

摘要翻译： 半导体工艺包括以下步骤。 提供基板。 栅极结构形成在衬底上。 在栅极结构旁边的衬底上形成间隔物。 间隔件包括第一间隔件和位于第一间隔件的外表面上的第二间隔件。 执行第一蚀刻工艺以蚀刻并在衬垫旁边的至少一个衬底中形成凹槽，并且完全除去第二间隔物。 第一蚀刻工艺对第一间隔物的蚀刻速率低于第一蚀刻工艺对第二间隔物的蚀刻速率。 在凹部中形成外延层。