公开(公告)号：US08581756B1

公开(公告)日：2013-11-12

申请号：US13628805

申请日：2012-09-27

Applicant: Cirrus Logic, Inc.

Inventor： Bruce Duewer ,  Gautham Devendra Kamath

IPC: H03M7/00

CPC classification number: H03H17/0223 ,  H03H17/0294 ,  H03H2017/0245 ,  H03M3/32 ,  H03M3/344 ,  H03M3/504

Abstract: A digital signal processing circuit, such as a digital-to-analog converter (DAC) having multiple cascaded processing stages, some of which are selectably placed in a low-power non-operating state according to a lower-power operating mode of the digital signal processing circuit and are placed in an operating state according to another higher-performance operating mode of the circuit. The output sample rates of the stages differ, so that the sample rate through the cascade changes. A signal characteristic determination block generates an indication of one or both of an amplitude and/or frequency of the input signal, so that the operating mode of the digital signal processing circuit is selected in conformity with the indication of amplitude and/or frequency of the input signal.

Abstract translation: 数字信号处理电路，例如具有多个级联处理级的数模转换器（DAC），其中一些数字信号处理电路根据数字的低功率操作模式可选地置于低功率非工作状态 信号处理电路，并且根据电路的另一个更高性能的操作模式被置于操作状态。 阶段的输出采样率不同，使得通过级联的采样率发生变化。 信号特征确定块产生输入信号的幅度和/或频率中的一个或两个的指示，使得数字信号处理电路的操作模式被选择为符合幅度和/或频率的指示 输入信号。