公开(公告)号：US11354182B1

公开(公告)日：2022-06-07

申请号：US16872606

申请日：2020-05-12

Applicant: Cisco Technology, Inc.

Inventor： Gaurav Gupta ,  Sachin Naik ,  Stefan Martin Schaeckeler ,  Surajit Ghoshal ,  Titian Lau

IPC: G06F11/07 ,  G06F11/14

Abstract: According to some embodiments, a system comprises a computer system comprising a processing unit, an interrupt controller, an internal watchdog, and a computer system reset interface. The system further comprises a watchdog controller comprising a secondary watchdog timer. Expiry of the computer system internal watchdog triggers the interrupt controller to cause the processing unit to collect debug information and triggers the watchdog controller to start a secondary watchdog timer. Expiry of the secondary watchdog timer triggers the watchdog controller to reset the computer system.