公开(公告)号：US20170244637A1

公开(公告)日：2017-08-24

申请号：US15048469

申请日：2016-02-19

Applicant: Citrix Systems, Inc.

Inventor： Pravin Singhal ,  Daisy Caroline Francis ,  Hrushikesh Shrinivas Paralikar

IPC: H04L12/743 ,  H04L29/12

CPC classification number: H04L45/7453 ,  H04L61/2514

Abstract: The present disclosure is directed towards systems and methods routing network packets between multi-core intermediaries. A processor of a plurality of processors on a client-side intermediary device may receive a packet from a client device. The processor may be identified by a core identifier. The processor may calculate a first set of source port addresses based on a first key and the core identifier. The processor may identify a target server-side intermediary device and a target processor based on data received with the packet or metadata received from the target server-side intermediary device. The processor may calculate a second set of port addresses based on a second key and the target core identifier. The processor may identify a port address common to both the first set and second set of port addresses. The processor may replace the original source port address in the packet with the identified port address.

公开(公告)号：US10333846B2

公开(公告)日：2019-06-25

申请号：US15048469

申请日：2016-02-19

Applicant: Citrix Systems, Inc.

Inventor： Pravin Singhal ,  Daisy Caroline Francis ,  Hrushikesh Shrinivas Paralikar

IPC: G06F15/173 ,  H04L12/743 ,  H04L29/12

Abstract: The present disclosure is directed towards systems and methods routing network packets between multi-core intermediaries. A processor of a plurality of processors on a client-side intermediary device may receive a packet from a client device. The processor may be identified by a core identifier. The processor may calculate a first set of source port addresses based on a first key and the core identifier. The processor may identify a target server-side intermediary device and a target processor based on data received with the packet or metadata received from the target server-side intermediary device. The processor may calculate a second set of port addresses based on a second key and the target core identifier. The processor may identify a port address common to both the first set and second set of port addresses. The processor may replace the original source port address in the packet with the identified port address.