NEURAL NETWORK ARCHITECTURE FOR A SYSTOLIC PROCESSOR ARRAY AND METHOD OF PROCESSING DATA USING A NEURAL NETWORK

    公开(公告)号:US20240232573A1

    公开(公告)日:2024-07-11

    申请号:US18395207

    申请日:2023-12-22

    IPC分类号: G06N3/04

    CPC分类号: G06N3/04

    摘要: The present disclosure relates to an electronic circuit implementing a neural network, the electronic circuit comprising: an array of processing elements (PE) implementing one or more neurons of the neural network, each processing element comprising a data processing circuit, and a local memory configured to store neuron data; and data propagation circuitry configured to perform forward or reverse lateral mixing of the neuron data by propagating, synchronously by each processing element, the neuron data to the local memory of each processing element from the local memory of one or more neighboring processing elements, wherein each of the processing elements is configured to process, during a first processing iteration, the neuron data from the one or more neighboring processing elements in order to generate updated neuron data and to store the updated neuron data in the local memory for use during a subsequent processing iteration.